zynq 多时钟输出

pll.v

`timescale 1ns / 1ps



module pll_test(

input  sys_clk,
input  rst_n,
output clock_out1,
output clock_out2,
output clock_out3,
output clock_out4

);

wire pll_locked;



clk_wiz_0 ins
   (
    // Clock out ports
    .clk_out1(clock_out1),     // output clk_out1
    .clk_out2(clock_out2),     // output clk_out2
    .clk_out3(clock_out3),     // output clk_out3
    .clk_out4(clock_out4),     // output clk_out4
    // Status and control signals
    .reset(~rst_n), // input reset
    .locked(pll_locked),       // output locked
   // Clock in ports
    .clk_in1(sys_clk));      // input clk_in1
endmodule

pll_testbench.v

`timescale 1ns / 1ps

module pll_testbench;


reg sys_clk;
reg rst_n;

wire clock_out1;
wire clock_out2;
wire clock_out3;
wire clock_out4;

pll_test pll_test(
.sys_clk (sys_clk),
.rst_n     (rst_n    ),
.clock_out1 (clock_out1),
.clock_out2 (clock_out2),
.clock_out3 (clock_out3),
.clock_out4 (clock_out4)
       )  ;


initial
begin 
sys_clk=1'b0;
rst_n  =1'b0;

#20 rst_n  =1'b1;
end
always  #10 sys_clk=~sys_clk;
endmodule