Verilog HDL建模(带VDD&VSS）——转发

【Verilog HDL】基础知识之开关级建模

//设计块
module CMOS_nor(out, a, b);
    input a, b;
    output out;
    
    //定义电源
    supply1 Vdd;
    supply0 Gnd;
    
    //实例化PMOS开关
    pmos (c, Vdd, b);
    pmos (out, c, a);
    
    nmos (out, Gnd, a);
    nmos (out, Gnd, b); 
endmodule

//激励块
module tb_CMOS_nor();
    reg A, B;
    wire OUT;
    
    CMOS_nor nor1(.out(OUT), .a(A), .b(B));
    
    initial begin
        A = 1'b0;
        B = 1'b0;
        #10 A = 1'b0;  B = 1'b1;
        #10 A = 1'b1;  B = 1'b0;
        #10 A = 1'b1;  B = 1'b1;
    end
    
    initial 
        $monitor($time ,"OUT = %b, A = %b, B = %b", OUT, A, B);
 
endmodule

//设计块
module mux2_1(out, s, in0, in1);
 
output out;
input  s, in0, in1;
 
wire sbar;  //s的取反
 
not (sbar, s);
 
cmos(out, in0, sbar, s);
cmos(out, in1, s, sbar);
endmodule

//程序块
//定义CMOS反相器
module CMOS_not(out, in);
 
    output out;
    input  in;
    supply1 Vdd;
    suppiy0 Gnd;
    
    pmos(out, Vdd, in);
    nmos(out, Gnd, in);
endmodule
 
//定义CMOS锁存器
module cff(q, qbar, d, clk);
 
    output q, qbar;
    input d, clk;
    
    wire e;
    wire nclk;
 
    CMOS_not nt1(nclk, clk);
 
    cmos(e, d, clk, nclk);
    cmos(e, q, nclk, clk);
endmodule