IDELAYCTRL的例化与使用

ERROR: [Drc 23-20] Rule violation (PLIDC-8) IDELAYCTRL DRC Checks - The IODELAY instance <> port’ has no associated IDelayCtrl. IDELAYCTRL instance is required to calibrate IODELAY instances.

This error is displayed if the user has instantiated more than one IDELAY_CTRL and has not applied LOC constraints to them.

If more than one is being used then Vivado cannot replicate the IDELAY_CTRLs and place them as required.

The user is required to ensure that there are enough IDELAY_CTRL instances for all of the banks that use the IODELAYs and that the following LOC constraint is applied to them.

set_property LOC IDELAYCTRL_X?Y? [get_cells <<instance_name>>/idelayctrl.delayctrl]
X?Y? in the above correspond to the clock region the I/O pins are located in.

To find the Clock Region, view the Device View in Vivado:

++++++++++++++++++++++++++++++++++++++++++++++++++++++
How to guide replication of IDELAYCTRL in Vivado when only one IDELAYCTRL is used in the design

If you are using IDELAYs / ODELAYs in multiple banks, then an IDELAYCTRL is required for each bank.

However, you can use Vivado to replicate the IDELAYCTRL by including one IDELAYCTRL at the top level.

You can guide the Vivado replication by creating generic IODELAY_GROUP constraints.

These place the one IDELAYCTRL and all IDELAYs into you group.

An example of the XDC syntax is below:

set_property IODELAY_GROUP IO_DLY1 [get_cells idelayctrl]
set_property IODELAY_GROUP IO_DLY1 [get_cells -hier idelaye2]

在工程中例化2个相同的IDELAYCTRL会报如下错误：

IDELAYCTRL not LOC or grouped

将2个模块中的IDELAYCTRL提取出来，放到顶层中，例化一个，error解决。

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

IDELAYCTRL 模块是为IDELAY模块服务的。DDR2中的u_iodelay_dq_ce用到了IDELAY模块，也就需要相应的IDELAYCTRL。但在改变约束文件里的IO loction时，它的位置约束要手动更改。
我是利用planahead来确定IDELAYCTRL的loction的。
在device的视图中，找到约束文件中所定义的IDELAY的位置，就是下图橙色的方块。在它的附近找到IDELAYCTRL，图中白色的矩形，读出它的位置信息，再添到你的约束文件里就好了。DDR2总共要3个IDELAYCTRL。

我需要实例化一个或多个IDELAYCTRL，我的选项是（1）实例化其中一个，并让toolfix一切，或者（2）实例化大量的，并且完成所有操作。

ug190的第342页说“使用IDELAYCTRL模块的最有效方法是定义和锁定设计中使用的每个IDELAYCTRL实例的位置… xilinx强烈建议使用带有LOC约束的IDELAYCTRL”

+++++++++++++++++++++++++++++++++++++++++++++++
AR# 64542

ERROR: [Drc 23-20] Rule violation (PLIDC-3) when instantiating the same SelectIO Wizard IP core several times
When instantiating multiple instances of the same SelectIO Wizard IP core, the following error might be displayed:
ERROR: [Drc 23-20] Rule violation (PLIDC-3) IDELAYCTRL DRC Checks - IDELAYCTRL instances ‘<SelectIO wizard IP hierarchical name #1>/inst/delayctrl’ and ‘<SelectIO wizard IP hierarchical name #2>/inst/delayctrl’ have same IODELAY_GROUP ‘_group’ but their REFCLK signals are different.
The SelectIO Wizard IP core contains IODELAY_GROUP constraints in the HDL code which is common for all instances.
(* IODELAY_GROUP = “selectio_wiz_0_group” *)
Because all instances use the same HDL code, but have different signals, this DRC error is issued.

To work around this issue you will need to edit the IODELAY_GROUP constraint in HDL and over-ride it with XDC constraints.
To edit the HDL open the _selectio_wiz.v file and search for the (* IODELAY_GROUP = “selectio_wiz_0_group” *) lines.

There will be one for the DELAY and another for the IDELAYCTRL. Comment out each of these lines as you are going to constrain the groups in the XDC file.

Then in the XDC file create an IODELAY_GROUP for each instance of the SelectIO Wizard.

The constraints can be kept generic, so all delay elements (IDELAYCTRL and IODELAY primitive) in an instance are constrained to the same group.

set_property IODELAY_GROUP _group1 [get_cells <SelectIO wizard IP hierarchical name #1>/inst/delay]
set_property IODELAY_GROUP _group2 [get_cells <SelectIO wizard IP hierarchical name #2>/inst/delay]

1.使用set_property IS_MANAGED false [get_files selectio_iddr.xci]，将selectio变为可读写

2.修改XXX_selectio_wiz.v文件，将 (* IODELAY_GROUP = “selectio_wiz_0_group” *) 给注释了

3.在自己的xdc文件里面加上set_property IODELAY_GROUP _group1 [get_cells <SelectIO wizard IP hierarchical name #1>/inst/delay]，要例化几个selectio，就要写几个group
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
CameraLink LVDS这个模块里使用了IDELAYCTRL和IODELAY，如果你的设计里有超过1个IDELAYCTRL cell，那么需要将每个IDELAYCTRL跟它所管辖的IODELAY cells约束为一个IODELAY_GROUP，这样工具才能正确的安排他们的布局。

你可以试试这么做：

1. 综合后open synthesized design，用edit -> find查找设计里所有的IDELAYCTRL和IDELAY

2. 根据cell名字里的层次关系，找出同一个CameraLink LVDS模块里的IDELAYCTRL和IDELAY

3. 在xdc里，给同一个模块里的IDELAYCTRL和IDELAY cells加相同的IODELAY_GROUP约束

set_property IODELAY_GROUP <group_name> [get_cells xxxx]

具体IODELAY_GROUP的用法看UG903，以及对应器件的selectio resource user guide

二、IDELAYCTR的使用

如果IOBDELAY_TYPE属性被设置为FIXED或者VARIABLE，则必须在代码中例化IDELAYCTRL模块，IDELAYCTRL模块在其区域里连续标定各个延迟单位，简单总结下IDELAYCTRl的使用方法。

（1） 无LOC约束的IDELAYCTRL

当例化无LOC约束的IDELAYCTRL时，HDL代码中必须只例化一个IDELAYCTRL实例，ISE实现时会自动复制到整个器件的延迟单元时钟区域当中，这样每一个时钟区域都有消耗一个全局时钟资源比，使用的布局布线资源也比较高，进而使得芯片的功耗也比较大。

当忽略RDY端口时，所以复制的IDELAYCTRL实例的RDY信号均不连接，但是当连接RDY端口时，例化一个宽度等于时钟区域数的与门，ISE实现时会自动连接到已经例化的所有IDELAYCTRL实例的RDY端口的信号与门输出。

（2） 有LOC约束的IDELAYCTRL

使用IDELAYCTRL模块最有效的方法是定义并且锁定代码中例化的所有的IDELAYCTRL实例的位置，Xilinx官方推荐在使用延迟单元时，应该定义并且锁定所有的ISERDES和IDELAY元件的位置，使用有LOC约束的IDELAYCTRL

添加有LOC的IDELAYCTRL需要注意：

一个IDELAYCTRL基元可同时覆盖一个clock region，而一个clock region包含不止一个IOB，在约束IDELAYCTRL基元LOC时，需要仔细定位该IOB属于哪个LOC的IDELAYCTRL。

（3） 位置约束

每一个IDELAYCTRL模块都有XY坐标位置，为了约束位置，IDELAYCTRL实例可以附带LOC属性，为IDELAYCTRL附加LOC属性可以在UCF文件中加入 INST “Instance name” LOC = IDELAYCTRL_X#Y#; 或者在HDL设计文件中直接嵌入LOC约束

下列语法用于在HDL设计文件中嵌入LOC约束。

// synthesis attribute loc of instance_name is “IDELAYCTRL_X#Y#”;

比如一个完整的实例:

IODELAY #(
.DELAY_SRC       ( "O"            ),    //IODELAY源是ODATAIN
.IDELAY_TYPE            ( "FIXED"   ),    //静态延迟
.ODELAY_VALUE ( 16             ),    //固定延迟数为16个tap
.REFCLK_FREQUENCY ( 200.0 )    //IDELAYCTRL参考时钟200MHz
)IODELAY_INST
 (
.C                       ( 1'b0          ),            //可变模式下使用的时钟输入
.CE                    ( 1'b0          ),            // 是否启动递增/递减功能
.DATAIN          ( 1'b0           ),  
.IDATAIN         ( 1'b0          ),
.INC                   ( 1'b0           ),           //tap延迟的递增/递减选择
.ODATAIN       ( LED          ),           //来自OLOGIC/OSERDES的信号
.RST                    ( 1'b0           ),
.T                         ( 1'b0           ),           //用作ODELAY
.DATAOUT      ( LED          )
);


IDELAYCTRL IDELAYCTRL_inst
 (
.RDY                 ( RDY                ), // 1-bit ready output
.REFCLK           ( System_Clk      ), // 1-bit reference clock input
.RST                   ( 1'b0                  ) // 1-bit reset input
);

+++++++++++++++++++++++++++++++++++++++++++++++++++
UG190
When instantiating IDELAYCTRL without LOC constraints, the user must instantiate only
one instance of IDELAYCTRL in the HDL design code.
The implementation tools autoreplicate IDELAYCTRL instances throughout the entire device.
When the RDY port is ignored, the RDY signals of all the replacement IDELAYCTRL
instances are left unconnected.
The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive
without LOC constraints leaving the RDY output port unconnected are provided in
the Libraries Guide.

When RDY port is connected, an AND gate of width equal to the number of clock
regions is instantiated and the RDY output ports from the instantiated and replicated
IDELAYCTRL instances are connected to the inputs of the AND gate. The tools assign
the signal name connected to the RDY port of the instantiated IDELAYCTRL instance
to the output of the AND gate.

The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive
without LOC constraints with the RDY port connected are provided in the Libraries
Guide.

The most efficient way to use the IDELAYCTRL module is to define and lock down the
placement of every IDELAYCTRL instance used in a design. This is done by instantiating
the IDELAYCTRL instances with location (LOC) constraints. The user must define and
lock placement of all ISERDES and IDELAY components using the delay element.
(IDELAY_TYPE attribute set to FIXED or VARIABLE). Once completed, IDELAYCTRL
sites can be chosen and LOC constraints assigned. Xilinx strongly recommends using
IDELAYCTRL with a LOC constraint. When not using an IDELAY (with IDELAY_TYPE in
FIXED or VARIABLE mode) do not assign a LOC constraint to the IDELAYCTRL for that
clock region.

Each IDELAYCTRL module has XY location coordinates (X:row, Y:column). To constrain
placement, IDELAYCTRL instances can have LOC properties attached to them. The
naming convention for IDELAYCTRL placement coordinates is different from the
convention used in naming CLB locations. This allows LOC properties to transfer easily
from array to array.

There are two methods of attaching LOC properties to IDELAYCTRL instances.
1 Insert LOC constraints in a UCF file
2 Embed LOC constraints directly into HDL design files
The Libraries Guide includes VHDL and Verilog use model templates for instantiating
IDELAYCTRL primitives with LOC constraints.

There are cases where the user instantiates an IDELAYCTRL module with a LOC
constraint but also instantiates an IDELAYCTRL module without a LOC constraint. In the
case where an IP Core is instantiated with a non-location constrained IDELAYCTRL
module and also wants to instantiate an IDELAYCTRL module without a LOC constraint
for another part of the design, the implementation tools will perform the following:

Instantiate the LOC IDELAYCTRL instances as described in the section Instantiating
IDELAYCTRL with Location (LOC) Constraints.

Replicate the non-location constrained IDELAYCTRL instance to populate with an
IDELAYCTRL instance in every clock region without a location constrained
IDELAYCTRL instance in place.

The signals connected to the RST and REFCLK input ports of the non-location
constrained IDELAYCTRL instance are connected to the corresponding input ports of
the replicated IDELAYCTRL instances.

If the RDY port of the non-location constrained IDELAYCTRL instance is ignored,
then all the RDY signals of the replicated IDELAYCTRL instances are also ignored.

If the RDY port of the non-location constrained IDELAYCTRL instance is connected,
then the RDY port of the non-location constrained instance plus the RDY ports of the
replicated instances are connected to an auto-generated AND gate. The
implementation tools assign the signal name connected to the RDY port of the nonlocation constrained instance to the output of the AND gate.

All the ports of the location constrained instances (RST, REFCLK, and RDY) are
independent from each other and from the replicated instances.

The VHDL and Verilog use models for instantiating a mixed usage model are provided in
the Libraries Guide. In the example, a user is instantiating a non-location constrained
IDELAYCTRL instance with the RDY signal connected. This discussion is also valid when
the RDY signal is ignored.

Instantiating multiple IDELAYCTRL instances without LOC properties is prohibited. If
this occurs, an error is issued by the implementation tools.