6位BCD十进制加法器verilog

module counter6bit_test(ENA,CLR,F_IN,Q);
input ENA;
input CLR;
input F_IN;
output [23:0] Q;

reg [23:0] Q;
reg F_OUT;

wire [4:0] temp;
wire[3:0] Q0,Q1,Q2,Q3,Q4,Q5;
wire f_cout;
bcd_count bc0(F_IN , CLR , ENA , temp[0] , Q0);
bcd_count bc1(F_IN , CLR , temp[0] , temp[1] , Q1);
bcd_count bc2(F_IN , CLR , temp[1] , temp[2] , Q2);
bcd_count bc3(F_IN , CLR , temp[2] , temp[3] , Q3);
bcd_count bc4(F_IN , CLR ,temp[3] , temp[4] , Q4);
bcd_count bc5(F_IN , CLR , temp[4] ,f_cout , Q5);

always @(*) begin
Q <= {Q5,Q4,Q3,Q2,Q1,Q0};
F_OUT <= f_cout;
end
endmodule

module bcd_count(
input clk,
input rst,
input en,
output reg cout,
output reg [3:0] res
);
always @(posedge clk)
begin
if(rst) res <= 4’b0000;
else begin
if(!en) res <= res;
else begin
if(res == 4’b1001) res <= 4’h0;
else res <= res+1’b1;
end
end
end

always @(*)

cout = (!rst) & en & (res == 4'b1001) ? 1 :0;

endmodule

其中，如果cout使用时序逻辑，
always @(posedge clk)

cout <= (!rst) & en & (res == 4'b1001) ? 1 :0;
这样会导致结果不对，原因是什么？