Xilinx FPGA RapidIO SRIO

最新推荐文章于 2025-04-30 12:33:42 发布

kunkliu

最新推荐文章于 2025-04-30 12:33:42 发布

阅读量1.3k

点赞数

CC 4.0 BY-SA版权

分类专栏： # zynq

原文链接：https://blog.youkuaiyun.com/Zhu_Zhu_2009/article/details/80635869?utm_source=blogxgwz5

zynq 专栏收录该内容

55 篇文章

订阅专栏

本文深入探讨了Xilinx的SRIO (Serial RapidIO) IP核配置与使用，详细介绍了SRIO IP的寄存器定义，包括Port General Control CSR、Base Device ID CSR、Host Base Device ID Lock CSR及Maintenance Request Information Register。此外，还解析了Processing Elements Features CAR的功能，为读者提供了全面的SRIO IP核应用指南。

摘要生成于 C知道，由 DeepSeek-R1 满血版支持，前往体验 >

参考

RapidIO规范《RapidIO_Rev_2.2_Specification》
书籍《RapidIO The Embedded System Interconnect》
Xilinx手册pg007《Serial RapidIO Gen2 Endpoint v4.1 LogiCORE IP Product Guide》
IDT CPS1848手册《CPS-1848™ User Manual》
博客Zynq-Linux移植学习笔记之14-RapidIO驱动开发
博客基于Xilinx的RapidIO核配置和AXI-SRIO核设计
系列博客SRIO学习
系列博客RapidIO（还介绍了TSI721）
Zynq—Linux移植学习笔记（十三）
Xilinx Srio详解&IP核使用
 SRIO系统初始化过程和路由配置

Xilinx Srio IP

Xilinx Srio IP的寄存器定义如下：

typedef struct/*total 16M*/
{
	/*Capability Register Space 0x00~0x3C*/
	unsigned int deviceIdentityCar;
	unsigned int deviceInfomationCar;
	unsigned int assemblyIdentityCar;
	unsigned int assemblyInfomationCar;
	unsigned int processingElementFeaturesCar;
	unsigned int switchPortInformationCar;
	unsigned int sourceOperationsCar;
	unsigned int destinationOperationsCar;
	unsigned int reservedCar[8];
	/*Command and Status Register Space 0x40~0xFC*/
	unsigned int reservedCsr1[3];
	unsigned int processingElementLogicalLayerCsr;
	unsigned int reservedCsr2[2];
	unsigned int localConfigurationSpaceBaseAddress0Csr;
	unsigned int localConfigurationSpaceBaseAddress1Csr;
	unsigned int baseDeviceIdCsr;
	unsigned int reservedCsr3;
	unsigned int hostBaseDeviceIdLockCsr;
	unsigned int componentTagCsr;
	unsigned int reservedCsr4[36];
	/*Extended Features Space default 0x100 ~ 0xFFFC*/
	/*    LP-Serial Extended Features block 0x100 ~ 0x1FC*/
	unsigned int lpSerialRegisterBlockHeader;
	unsigned int reservedEfs1[7];
	unsigned int portLinkTimeoutCsr;
	unsigned int portResponseTimeoutCsr;
	unsigned int reservedEfs2[5];
	unsigned int portGeneralControlCsr;
	unsigned int portNMaintenanceRequestCsr;
	unsigned int portNMaintenanceResponseCsr;
	unsigned int portNLocalAckIdCsr;
	unsigned int reservedEfs3[2];
	unsigned int portNControl2Csr;
	unsigned int portNErrorAndStatusCsr;
	unsigned int portNControlCsr;
	unsigned int reservedEfs4[40];
	/*    reserved 0x200~0x3FC*/
	unsigned int reservedEfs5[192];
	/*    LP-Serial Lane Extended Features block 0x400~0x4FC*/
	unsigned int lpSerialLaneRegisterBlockHeader;
	unsigned int reservedEfs6[3];
	unsigned int lane0Status0Csr;
	unsigned int lane0Status1Csr;
	unsigned int reservedEfs7[6];
	unsigned int lane1Status0Csr;
	unsigned int lane1Status1Csr;
	unsigned int reservedEfs8[6];
	unsigned int lane2Status0Csr;
	unsigned int lane2Status1Csr;
	unsigned int reservedEfs9[6];
	unsigned int lane3Status0Csr;
	unsigned int lane3Status1Csr;
	unsigned int reservedEfs10[34];
	/*reserved 0x500~0xFFFC*/
	unsigned int reserved1[16064];
	/*Implementation-defined Space 0x10000~0xFFFFFC*/
	unsigned int watermarksCsr;
	unsigned int bufferControlCsr;
	unsigned int reservedIds[62];
	unsigned int maintenanceRequestInfomationRegister;
	/*reserved */
	unsigned int reserved2[0];
} __attribute__((packed, aligned(4))) SRIOREG, *PSRIOREG;

 
 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66

列举用到的4个寄存器，详细参考pg007。

Port General Control CSR，使能Master Enable。
Base Device ID CSR，设置器件ID，host可设为1，默认值在vivado里设置。
Host Base Device ID Lock CSR，器件锁定寄存器，复位之后，这个寄存器只能被写一次（之后被锁定），配置之后如果写入值和寄存器值相等，则寄存器值被复位为0xFFFF，向该寄存器写入0xFFFF不会锁定寄存器。
Maintenance Request Information Register，维护包配置寄存器，地址在0x10100，低16位用于配置目的ID，当用IP发维护包之前，需要配置这个寄存器。
Processing Elements Features CAR，表示这个设备提供的功能，可以是Bridge，Memory，Processor，Switch 4种，SRIO IP支持前3种（endpoint），支持16位地址模式，可在vivado中通过GUI设置。