fpga系列 HDL：verilog 常见错误与注意事项 Can‘t resolve multiple constant drivers for net+has mixed blocking and

Error (10028): Can’t resolve multiple constant drivers for net “ro” at top.v(17)

• 错误信息 Can’t resolve multiple constant drivers for net “ro” at top.v(17) 表明在Verilog代码中，信号ro被多个常量驱动源（constant drivers）同时赋值。这种情况会导致合成工具无法确定哪个赋值应该生效，从而产生冲突。

错误示例

module top(
		  input wire Clk,
        input wire a,
        input wire b,
        input wire en1,
        input wire en2,
        output wire o
);
        
        reg ro;
        
        always@(posedge Clk)begin
			  if(en1)
						 ro <= a;      
        end
        always@(posedge Clk)begin
			  if(en2)
						 ro <= b;        
        end  
        assign o = ro;

endmodule

修正

module top(
		  input wire Clk,
        input wire a,
        input wire b,
        input wire en1,
        input wire en2,
        output wire o
);
        
        reg ro;
        
        always@(posedge Clk)begin
        if(en1)
                ro <= a;
		  if(en2)
                ro <= b;        
        end    
                
        assign o = ro;

endmodule

10110 Verilog HDL error at : variable “” has mixed blocking and nonblocking Procedural Assignments – must be all blocking or all nonblocking assignments

• 错误原因variable "<name>"在程序中有时用非阻塞赋值，有时用阻塞赋值。注：在仿真和设计文件中可以使用不同赋值