3.1.3 Arithmetic Circuits
3.1.3.1 Hadd
module top_module(
input a, b,
output cout, sum );
assign {cout,sum} = a + b;
endmodule
3.1.3.2 Fadd
module top_module(
input a, b, cin,
output cout, sum );
assign {cout,sum} = a + b + cin;
endmodule
3.1.3.3 3-bit binary adder
1-bit加法器例化成一个3-bit加法器
module top_module(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
wire tmp1,tmp2,tmp3;
fdder one (a[0],b[0],cin,tmp1,sum[0]);
fdder two (a[1],b[1],tmp1,tmp2,sum[1]);
fdder three (a[2],b[2],tmp2,tmp3,sum[2]);
assign cout = {tmp3,tmp2,tmp1};
endmodule
module fdder(
input a,
input b,
input cin,
output cout,
output sum
);
assign {cout,sum} = a + b + cin;
endmodule
3.1.3.4 Adder
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum);
assign sum = x + y;
endmodule
3.1.3.5 Adder
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
assign s = a + b;
assign overflow = (a[7] & b[7] & ~s[7]) | (~a[7] & ~b[7] & s[7]);
// assign s = ...
// assign overflow = ...
endmodule
a[7]和b[7]分别是两个加数的符号为,s[7]是运算结果的符号位
当a[7] = b[7] = 0(两数同为正数), s[7]= 1(结果为负数)时,有溢出
当a[7] = b[7] = 1(两数同为负数), s[7]= 0(结果为正数)时,有溢出
即,若运算结果的符号位与原来加数的符号位不同时,有溢出
3.1.3.6 100-bit binary adder
module top_module(
input [99:0] a, b,
input cin,
output cout,
output [99:0] sum );
assign {cout,sum} = a + b + cin;
endmodule
3.1.3.7 4-digital BCD adder
module top_module(
input [15:0] a, b,
input cin,
output cout,
output [15:0] sum );
wire [2:0] tmp;
bcd_fadd adder0 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.cout(tmp[0]),
.sum(sum[3:0])
);
bcd_fadd adder1 (
.a(a[7:4]),
.b(b[7:4]),
.cin(tmp[0]),
.cout(tmp[1]),
.sum(sum[7:4])
);
bcd_fadd adder2 (
.a(a[11:8]),
.b(b[11:8]),
.cin(tmp[1]),
.cout(tmp[2]),
.sum(sum[11:8])
);
bcd_fadd adder3 (
.a(a[15:12]),
.b(b[15:12]),
.cin(tmp[2]),
.cout(cout),
.sum(sum[15:12])
);
endmodule