HDLbits答案刷题记录1

3.1.1 Basic gates

3.1.1.8 Truth table

• 组合逻辑电路中输出仅仅是其输入的函数（在数学意义上）

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);
    assign f = (x3 & x1) | (x2 & x1) | ((~x3) & x2);
endmodule

3.1.1.9 Two-bit equality

module top_module (
	 input [1:0] A,
	 input [1:0] B,
	 output z
); 
    assign z = (A == B) ? 1 : 0;
endmodule

3.1.1.10 Sample circuit A

module top_module (input x, input y, output z);
    assign z = (x ^ y) & x;
endmodule

3.1.1.11 Sample circuit B

module top_module ( input x, input y, output z );
	assign z = x ~^ y;
endmodule

3.1.1.12 Combine circuit A and B

module top_module (input x, input y, output z);
	wire t