4,verilog仿真语法模版_过程块语句

Procedural blocks

1.Always条件过程块（conditional repeated execution）  

 always @(<signals>) begin

      <statements>;

   end

2.initial过程块（execute once）  

 initial begin

      //  Wait for Global Reset to Complete

      #100;

      <statements>;

   end               

3.always持续过程块（repeated execution）

   always begin

      <statements>;

         end

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