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RSS订阅原创 HDLBits 计数器
HDLBitsCount15Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.module top_module ( input clk, input reset, // Synchronous act
2022-02-14 13:18:53
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原创 HDLBits 移位寄存器
HDLBitsShift4Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.areset: Resets shift register to zero. load: Loads shift register withdata[3:0]instead of shifting. ena: Shift right (q[3]becomes zero...
2022-01-30 18:22:30
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原创 HDLBits 时序逻辑电路（锁存与触发）
HDLBitsDffCreate a single D flip-flop.module top_module ( input clk, // Clocks are used in sequential circuits input d, output reg q );// always @(posedge clk) q <= d; // Use a clocked always block // copy d
2022-01-27 14:41:43
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原创 verilog练习笔记 （语法特征）
HDLBitsConditionalVerilog has a ternary conditional operator ( ? : ) much like C:(condition ? if_true : if_false)This can be used to choose one of two values based on condition (a mux!) on one line, without using an if-then inside a combinational a
2022-01-03 09:09:07
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原创 verilog学习笔记（过程语句）
HDlBits ProceduresAlwaysblock1:A bit of practice:Build an AND gate using both an assign statement and a combinational always block.// synthesis verilog_input_version verilog_2001module top_module( input a, input b, output wire out_
2021-12-30 16:43:54
853
原创 verilog向量练习
HDLBits 向量Vector0module top_module( input [2:0] vec, output [2:0] outv, output o2, output o1, output o0); assign outv = vec; // This is ok too: assign {o2, o1, o0} = vec; assign o0 = vec[0]; assign o1 = vec[1]; assign o2 = vec[2]; e
2021-12-29 10:39:41
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原创 verilog学习笔记（模块module）
HDLBits Module模块调用方法By positionmod_a instance1 ( wa, wb, wc ); 通过端口位置一一对应，以此来实现两个模块之间的连接，但当其中一个模块的端口位置发生改变，就需要对相应连接的线进行重新连接。及线连接的对象会因为端口位置的变化而变化。By namemod_a instance2 ( .out(wc), .in1(wa), .in2(wb) ); 该方法是...
2021-12-28 15:37:05
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原创 verilog学习笔记（HDLbits基础篇）
HDLbits（verilog练习网站）拼接运算符运算符号： {}功能： 将两个或多个信号的某些为拼接起来。 {信号1的某几位，信号2的某几位……信号n的某几位} 如：{3{a,b}} = {{a,b},{a,b},{a,b}} = {a,b,a,b,a,b};图例：代码实现：//非拼接运算附值办法module top_module ( input a, input b, input c...
2021-10-06 16:04:54
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