Verilog刷题-10-Wire_dec

题目描述

• 文字描述
  The circuits so far have been simple enough that the outputs are simple functions of the inputs. As circuits become more complex, you will need wires to connect internal components together. When you need to use a wire, you should declare it in the body of the module, somewhere before it is first used. (In the future, you will encounter more types of signals and variables that are also declared the same way, but for now, we’ll start with a signal of type wire).
  简单来说，就是进行wire类型变量的声明。
• 需要声明wire变量电路图示
  
• 对应的代码

  module top_module (
      input in,              // Declare an input wire named "in"
      output out             // Declare an output wire named "out"
  );
  
  wire not_in;           // De