Verilog 刷题-Exams/m2014 q4j

用了一种投机取巧的方式，也可以说是违背了这道题想要我们解题的方法。

就是跟上题一样，将四个全加器级联。

特别地，把最后一位全加器的输出作为sum的最后一位。

module adder(
    input a,b,cin,output cout,sum);
    assign cout = (a&b)|(a&cin)|(b&cin);
    assign sum = a^b^cin;
endmodule

module top_module (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
    );
    wire [3:0]cout;
    
    adder a1(.a(x[0]),.b(y[0]),.cin(),.cout(cout[0]),.sum(sum[0]));
    adder a2(.a(x[1]),.b(y[1]),.cin(cout[0]),.cout(cout[1]),.sum(sum[1]));
    adder a3(.a(x[2]),.b(y[2]),.cin(cout[1]),.cout(cout[2]),.sum(sum[2]));
    adder a4(.a(x[3]),.b(y[3]),.cin(cout[2]),.cout(cout[3]),.sum(sum[3]));
   assign sum[4] = cout[3];
endmodule

 看完参考答案，感觉自己小丑了。

module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);

	// This circuit is a 4-bit ripple-carry adder with carry-out.
	assign sum = x+y;	// Verilog addition automatically produces the ca