HDLBits

题目__Bcdadd100

You are provided with a BCD one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.

module bcd_fadd (
    input [3:0] a,
    input [3:0] b,
    input     cin,
    output   cout,
    output [3:0] sum );

Instantiate 100 copies of bcd_fadd to create a 100-digit BCD ripple-carry adder. Your adder should add two 100-digit BCD numbers (packed into 400-bit vectors) and a carry-in to produce a 100-digit sum and carry out.

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
    
   
    wire [99:0] cout_t;
    bcd_fadd bcd_0(.a(a[3:0]),.b(b[3:0]),.cin(cin),.cout(cout_t[1]),.sum(sum[3:0]));
    generate 
        genvar i;
        for(i=2;i<100;i++)
            begin:bcd_fadd_1
                bcd_fadd bcd(
                    		 .a        (a[(4*i-1):4*(i-1)]),
                             .b        (b[(4*i-1):4*(i-1)]),
                             .cin      (cout_t[i-1]),
                             .cout     (cout_t[i]),
                             .sum      (sum[(4*i-1):4*(i-1)]));			  
            end
           
    endgenerate
    bcd_fadd bcd_99(.a(a[399:396]),.b(b[399:396]),.cin(cout_t[99]),.cout(cout),.sum(sum[399:396]));
    

endmodule

题目__Gatesv100

See also the shorter version: Gates and vectors.

You are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit and its neighbour:

• out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left are '1'. For example, out_both[98] should indicate if in[98] and in[99] are both 1. Since in[99] has no neighbour to the left, the answer is obvious so we don't need to know out_both[99].
• out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don't need to know out_any[0].
• out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[98] should indicate if in[98] is different from in[99]. For this part, treat the vector as wrapping around, so in[99]'sneighbour to the left is in[0].

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );
	assign out_both=in[99:1]&in[98:0];
    assign out_any=in[99:1]|in[98:0];
    
    assign out_different=in^{in[0],in[99:1]};
endmodule

题目__Mux256to1v

Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.

 

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    
    assign out={in[4*sel+3],in[4*sel+2],in[4*sel+1],in[4*sel]};
   
endmodule

HDLBits答案 

module top_module (
	input [1023:0] in,
	input [7:0] sel,
	output [3:0] out
);

	
	assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};

	
	// assign out = in[sel*4 +: 4];		// Select starting at index "sel*4", then select a total width of 4 bits with increasing (+:) index number.
	// assign out = in[sel*4+3 -: 4];	// Select starting at index "sel*4+3", then select a total width of 4 bits with decreasing (-:) index number.
	// Note: The width (4 in this case) must be constant.

endmodule