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RSS订阅原创 RAM / SRAM /PSRAM /DRAM的区别
摘要：RAM分为SRAM、DRAM和PSRAM三种类型。SRAM由4-6个晶体管组成，速度快但成本高，主要用于CPU缓存；DRAM采用1晶体管+1电容结构，容量大成本低但需刷新，用于主内存；PSRAM本质是DRAM但集成刷新电路，具有类似SRAM的简单接口，适用于低成本嵌入式系统。三者在速度、成本和接口复杂度上各具特点：SRAM最快最贵，DRAM容量最大，PSRAM则平衡了成本与易用性。
2025-11-13 11:56:08
616
原创 数字电源和模拟电源隔离的原理
摘要：数字与模拟电路电源隔离的核心在于阻断开关噪声传播。数字电路工作时产生的大电流脉冲会通过电源网络干扰敏感的模拟电路。隔离方法包括：1）划分独立电源域；2）PCB物理分区布局和单点接地；3）使用LC滤波器、磁珠和去耦电容；4）采用独立电源转换器或隔离模块。信号隔离可串联电阻或使用光耦。通过"分域-单点连接-滤波-源头隔离"的系统方法，可有效保护模拟电路的供电环境，确保系统性能（150字）。
2025-10-13 19:06:46
1242
原创 协议学习番外篇 -- 全双工
UART通过独立TX/RX线实现全双工通信，允许数据同时双向传输。其硬件包含独立的发送器和接收器，支持同步收发操作。相比半双工和单工模式，全双工效率更高，典型应用包括单片机调试和蓝牙模块。其他常见全双工协议还有SPI、USB和以太网等，而I²C、CAN等则为半双工。理解全双工特性对设计高效通信系统至关重要。
2025-10-13 15:55:05
528
原创 串行通信的基石：UART与USART
UART和USART是两种常用的串行通信接口。UART是通用异步收发传输器，采用异步通信方式，通过TX/RX双线实现全双工通信，无需时钟信号，硬件简单成本低。USART是UART的超集，支持同步/异步两种模式，同步模式下需额外时钟线，通信更可靠。两者均采用标准数据帧结构（起始位+数据位+停止位），需配置相同波特率。UART广泛用于GPS、蓝牙等模块，USART适用于高速可靠通信场景。理解这两种接口对于嵌入式系统开发至关重要。
2025-10-13 15:39:02
1260
原创 开篇 -- 罗列常见常用的各种协议接口
罗列下各种常见常用的协议接口，也算是做个计划，后续按照这个罗列来依次输出，算是个总的目录吧；暂时想到的就这些，后面再想到或者接触到其他的另外更新吧。
2025-10-13 13:58:18
35
原创 HDLbits 刷题 -- Exams/m2014 q3
(原试题要求简化该函数的SOP和POS形式。考虑下面卡诺图中显示的函数f。分析：四个角的位置可以圈在一起。
2024-05-10 19:16:16
346
原创 HDLbits 刷题 -- Exams/m2014 q3
Exams/m2014 q3 Consider the functionfshown in the Karnaugh map below.
2024-05-09 19:11:40
392
原创 HDLbits 刷题 -- Exams/ece241 2013 q2
一个计算POS的偷懒方法： 先按照SOP的形式写出式子（是否取反按照POS的概念来定），简化后，再将各输入之间的与改为或，各输出之间的或改为与；- 在卡诺图中，SOP通常通过将1（真值）所在的单元格圈起来，然后找到这些圈能够覆盖的最小数量的单元格，每个圈代表一个AND门的乘积项。- 在卡诺图中，要得到POS形式，可以想象将SOP形式中的1和0互换，然后再次应用SOP的圈定方法，得到的圈将代表OR门的求和项。”，是一种将逻辑函数表示为AND（与）门的输出进行OR（或）连接的形式。
2024-05-09 19:01:10
694
原创 HDLbits 刷题 -- Kmap4
mplement the circuit described by the Karnaugh map below.
2024-04-25 18:42:46
425
原创 HDLbits 刷题 -- Kmap3
Implement the circuit described by the Karnaugh map below.
2024-04-25 18:24:40
397
原创 HDLbits 刷题 -- Kmap2
Implement the circuit described by the Karnaugh map below.
2024-04-22 19:37:11
738
原创 HDLbits 刷题 -- Kmap1
mplement the circuit described by the Karnaugh map below.
2024-04-22 19:03:07
465
原创 HDLbits 刷题 -- Bcdadd4
You are provided with a BCD (binary-coded decimal) one-digit adder namedbcd_faddthat adds two BCD digits and carry-in, and produces a sum and carry-out.
2024-04-19 19:13:01
500
原创 HDLbits 刷题 -- Adder100
Create a 100-bit binary adder. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out.
2024-04-19 18:52:19
533
原创 HDLbits 刷题 -- Exams/ece241 2014 q1c
Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.
2024-04-18 19:29:11
656
原创 HDLbits 刷题 -- Exams/m2014 q4j
Exams/m2014 q4j Implement the following circuit:
2024-04-18 19:03:53
303
原创 HDLbits 刷题 -- Adder3
Now that you know how to build afull adder, make 3 instances of it to create a 3-bit binary ripple-carry adder. The adder adds two 3-bit numbers and a carry-in to produce a 3-bit sum and carry out. To encourage you to actually instantiate full adders, a
2024-04-17 19:00:46
1062
原创 HDLbits 刷题 -- Fadd
Create a full adder. A full adder adds three bits (including carry-in) and produces a sum and carry-out.
2024-04-17 18:48:24
457
原创 HDLbits 刷题 -- Hadd
Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.
2024-04-17 18:45:45
312
原创 HDLbits 刷题 --Mux256to1v
Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bitsin[3:0], sel=1 selects bitsin[7:4], sel=2 selects bitsin[11:8], etc.
2024-04-17 18:42:37
527
原创 HDLbits 刷题 -- Mux256to1
Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should selectin[0], sel=1 selects bitsin[1], sel=2 selects bitsin[2], etc.
2024-04-17 18:28:29
412
原创 HDLbits 刷题 -- Mux9to1v
Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.
2024-04-17 18:24:14
498
原创 HDLbits 刷题 --Mux2to1v
Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.
2024-04-16 19:34:06
551
原创 HDLbits 刷题 --Mux2to1
Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.
2024-04-16 19:21:31
319
原创 HDLbits 刷题 --Gatesv100
You are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit and its neighbour:
2024-04-16 19:05:59
618
原创 HDLbits 刷题 --Gatesv
You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour:
2024-04-15 18:43:16
641
原创 HDLbits 刷题 --Popcount3
A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 3-bit input vector.译：“人口计数”电路计算输入向量中“1”的数量。为一个3位输入向量建立一个人口计数电路。个人解法：官方解法：运行结果：
2024-04-12 18:26:46
671
3
原创 HDLbits 刷题 --Thermostat
A heating/cooling thermostat controls both a heater (during winter) and an air conditioner (during summer). Implement a circuit that will turn on and off the heater, air conditioning, and blower fan as appropriate.
2024-04-12 18:14:27
444
原创 HDLbits 刷题 -- Ringer
Suppose you are designing a circuit to control a cellphone's ringer and vibration motor. Whenever the phone needs to ring from an incoming call (inputring), your circuit must either turn on the ringer (outputringer= 1) or the motor (outputmotor= 1), b
2024-04-12 18:04:27
579
原创 HDLbits 刷题 --Mt2015 q4
Seemt2015_q4aandmt2015_q4bfor the submodules used here. The top-level design consists of two instantiations each of subcircuits A and B, as shown below.
2024-04-11 19:14:42
377
原创 HDLbits 刷题 --Mt2015 eq2
Create a circuit that has two 2-bit inputsA[1:0]andB[1:0], and produces an outputz. The value ofzshould be 1 ifA = B, otherwisezshould be 0.
2024-04-10 19:19:28
367
原创 HDLbits 刷题 --Truthtable1
In the previous exercises, we used simple logic gates and combinations of several logic gates. These circuits are examples of combinational circuits. Combinational means the outputs of the circuit is a function (in the mathematics sense) of only its inputs
2024-04-10 19:10:04
1221
原创 HDLbits 刷题 --7420
The 7400-series integrated circuits are a series of digital chips with a few gates each. The 7420 is a chip with two 4-input NAND gates.Create a module with the same functionality as the 7420 chip. It has 8 inputs and 2 outputs.
2024-04-10 18:50:33
345
原创 HDLbits 刷题 --Gates
Ok, let's try building several logic gates at the same time. Build a combinational circuit with two inputs,aandb.There are 7 outputs, each with a logic gate driving it:
2024-04-10 18:44:40
196
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