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RSS订阅原创 数字电路：常见的锁存器浅析
由于S-R/S'-R'锁存器在所有时间内对输入都是敏感的，我们期望有一种器件，它只有在使能输入C有效时，才对输入敏感，具有使能端的S-R锁存器(S-R latch with enable)应运而生。总之，作者认为，只要掌握了S-R锁存器，S'-R'锁存器只不过是将输入信号进行反转，我们通过相应的分析即可得出S'-R'锁存器的输出。总结，本次我们介绍了S-R锁存器，S'-R'锁存器，具有使能端的S'-R'锁存器，D锁存器。①S,R均为0，S-R锁存器相当于双稳态元件，通过反馈回路维持电路之前的状态。...
2022-08-17 12:58:27
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原创 【数电】【verilog】加法器
串行全加器是上面这样，但是这种结构的缺点是，必须要等到上一片的结果算出来之后下一片才能进行工作，当级数很高的时候计算的时间将是每一片时间的n倍，会出现组合逻辑延时过长的问题。此时另一种进位方法——超前进位加法器就可以解决这一延时过高的问题。这里实在看不懂可以翻一番数电的超前进位加法器的内容。超前进位加法器就是用电路的复杂度来换时间。3.4位串行加法器（全加器）verilog代码如下：0。1.2输入1bit半加器。2.2输入1bit全加器。4.4位超前进位加法器。...
2022-08-11 22:02:11
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原创 【HDLBits刷题】Countslow.
设计一个0～9的计数器，共10个周期。该计数器采用同步复位且复位为0。但是本题是希望该计数器并不是随着clk的变化而递增，而是随着一个slowena使能信号来控制增加。
2022-07-19 23:13:18
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原创 【HDLBits刷题】Dualedge..
You're familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge triggered flip-flops, and alwa
2022-07-12 22:54:59
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原创 【HDLBits刷题】Edgecapture..
For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).Each output bit behaves like a SR flip-flop: The o
2022-07-06 20:35:31
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原创 【HDLBits刷题】Edgedetect2.
For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.Here are some examples. For clarity, in[1] and anyedge[1] are
2022-07-06 12:14:28
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原创 【HDLBits刷题】Edgedetect.
For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.Here are some examples. For clarity,
2022-07-05 12:18:05
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原创 【HDLBits刷题】Exams/ece241 2013 q7.
A JK flip-flop has the below truth table. Implement a JK flip-flop with only a D-type flip-flop and gates. Note: Qold is the output of the D flip-flop before the positive clock edge.module top_module ( input clk, input j, input k, output Q
2022-07-04 21:33:34
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原创 【HDLBits刷题】Exams/ece241 2014 q4.
Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.Build this circuit.开始的时候置0，所以一开始所有的Q都得是0；这个地方放写完之后有个疑惑，就是w1、w2、w3是不是定义成reg类型会更好（reg类型是通过的） ，但是定义成wire类型也是通过了的：mod
2022-04-27 18:33:59
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原创 【HDLBits刷题】Exams/2014 q4a.
Consider the n-bit shift register circuit shown below:Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers.1、第一种方法是通过抽象方法，从电路最后面看，写出Q输出：module top_module ( input clk, input w, R
2022-04-27 12:17:39
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原创 【HDLBits刷题】Exams/m2014 q4d.
Implement the following circuit:图中有一个 D 触发器与一个异或门，触发器的输出 q 和输入信号 in 一起作为异或门的输入。异或门的输入作为触发器的输入 dmodule top_module ( input clk, input in, output reg out); always @(posedge clk) begin out <= in ^ out; endendmodule.
2022-04-25 22:51:14
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原创 【HDLBits刷题】Exams/m2014 q4c.
Implement the following circuit:写一个同步复位的D触发器module top_module ( input clk, input d, input r, // synchronous reset output q); always @(posedge clk)begin if(r) q <= 0; else q <= d;.
2022-04-25 21:51:38
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原创 【HDLBits刷题】Exams/m2014 q4b.
Implement the following circuit:AR 代表 asynchronous reset，所以这是一个带有异步复位的 D 触发器，我们在先前的题目中讨论过异步复位的问题。图中的三角形代表时钟，不再用 CLK 标出。module top_module ( input clk, input d, input ar, // asynchronous reset output q); always @(posedge c
2022-04-25 12:25:32
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原创 【数字电路】D锁存器和D触发器的区别
我们在数字电路中经常使用到D触发器，有时候还会听到D锁存器这种电路，那么这两种电路到底有什么关系？又存在什么区别？方法一：功能的文字叙述 1）D锁存器： 功能分析文字描述：C = 0时，输出状态保持不变；C = 1时，输出随输入状态而改变。 2）D触发器： 功能分析文字描述： CLK=0时，主锁存器工作，接收输入信号Qm = D；从锁存器不工作，输出 Q 保持不变。 CLK=1时，主锁存器不工作，Qm保持不变；从锁存器工作，将Qm传送到输出端。
2022-04-24 08:28:33
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原创 【HDLBits刷题】Exams/m2014 q4a.
Implement the following circuit:Note that this is a latch, so a Quartus warning about having inferred a latch is expected.做一个D触发器module top_module ( input d, input ena, output q); always @(*)begin if(ena) q = d
2022-04-24 08:00:12
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原创 【HDLBits刷题】Dff16e..
Create 16 D flip-flops. It's sometimes useful to only modify parts of a group of flip-flops. The byte-enable inputs control whether each byte of the 16 registers should be written to on that cycle. byteena[1] controls the upper byte d[15:8], while byteena[
2022-04-23 23:14:02
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原创 【HDLBits刷题】Dff8ar..
Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.要求创建一个异步清零端的D触发器module top_module ( input clk, input areset, // active high asynchronous reset input [7:0] d, output
2022-04-22 19:36:17
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原创 【HDLBits刷题】Dff8p.
Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk.实现具有高电平同步复位的8个D触发器，同时复位值为0x34，下降沿触发。module top_module ( input clk, input
2022-04-22 18:45:54
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原创 【HDLBits刷题】Dff8r
Create 8 D flip-flops with active high synchronous reset. All DFFs should be triggered by the positive edge of clk.写一个带reset高电平有效复位的D触发器（时钟是上升沿触发）另外最好把在过程语句中的变量设置成reg格式，比如此处的q。（赋值语句左边的）module top_module ( input clk, input reset, /
2022-04-21 22:45:19
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原创 【HDLBits刷题】Dff8
Create 8 D flip-flops. All DFFs should be triggered by the positive edge ofclk.module top_module ( input clk, input [7:0] d, output [7:0] q); always @(posedge clk) q <= d;endmodule
2022-04-21 22:24:09
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原创 【HDLBits刷题】Dff.
A D flip-flop is a circuit that stores a bit and is updated periodically, at the (usually) positive edge of a clock signal.D flip-flops are created by the logic synthesizer when aclocked always blockis used (Seealwaysblock2). A D flip-flop is the si...
2022-04-21 22:22:33
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原创 【HDLBits刷题】Exams/ece241 2014 q3.
For the following Karnaugh map, give the circuit implementation using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must useaandbas the multiple...
2022-04-21 22:19:17
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原创 【HDLBits刷题】Exams/ece241 2013 q2.
A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this syst
2022-04-20 22:10:35
3278
原创 【HDLBits刷题】Kmap4.
Implement the circuit described by the Karnaugh map below.Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if you
2022-04-20 20:59:05
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原创 【HDLBits刷题】Kmap3.
Implement the circuit described by the Karnaugh map below.Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if you
2022-04-20 20:39:59
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原创 【HDLBits刷题】Kmap2.
Implement the circuit described by the Karnaugh map below.Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if you
2022-04-20 12:22:17
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原创 【HDLBits刷题】Kmap1.
Implement the circuit described by the Karnaugh map below.Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if you
2022-04-19 23:31:23
735
原创 【HDLBits刷题】Bcdadd4.
You are provided with a BCD (binary-coded decimal) one-digit adder namedbcd_faddthat adds two BCD digits and carry-in, and produces a sum and carry-out.module bcd_fadd ( input [3:0] a, input [3:0] b, input cin, output cout, o..
2022-04-19 12:35:47
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原创 【HDLBits刷题】Adder100.
Create a 100-bit binary adder. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out.Expected solution length: Around 1 line.弄一个两个100-bit相加的全加器1、第一种module top_module( input [99:0] a, b, input cin, ou
2022-04-19 07:55:12
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原创 【HDLBits刷题】Exams/ece241 2014 q1c.
Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.本题讨论的是有符号数相加的溢出问题中，需要实现一个 2 进制 8bit 有符号数加法器，加法器将输入的两个 8bit数补码相加，产生相加之和以及进位。modul
2022-04-18 22:23:28
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原创 数字逻辑电路——原码，反码，补码
https://blog.youkuaiyun.com/qq_45838676/article/details/106146093
2022-04-18 22:17:32
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原创 【HDLBits刷题】Exams/m2014 q4j
Implement the following circuit:("FA" is a full adder)1、第一种，就是采用实例化模块的方式来进行：module top_module ( input [3:0] x, input [3:0] y, output [4:0] sum); wire cout0,cout1,cout2; fadd U1(x[0],y[0],0,cout0,sum[0]); fadd U2(x[1],y[1],
2022-04-18 12:28:45
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原创 【HDLBits刷题】Adder3.
Now that you know how to build afull adder, make 3 instances of it to create a 3-bit binary ripple-carry adder. The adder adds two 3-bit numbers and a carry-in to produce a 3-bit sum and carry out. To encourage you to actually instantiate full adders, als.
2022-04-17 23:17:54
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原创 【HDLBits刷题】Fadd.
Create a full adder. A full adder adds three bits (including carry-in) and produces a sum and carry-out.Expected solution length: Around 2 lines.1、第一种，拼接：module top_module( input a, b, cin, output cout, sum ); assign {cout,sum} = a + b
2022-04-17 22:43:51
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原创 【HDLBits刷题】Hadd.
Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.Expected solution length: Around 2 lines.1、第一种，利用拼接括号module top_module( input a, b, output cout, sum ); assign {cout,sum} = a + b;endm
2022-04-17 22:27:37
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原创 【HDLBits刷题】Mux256to1v.
Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.Expected solution length: Around 1–5 lines.
2022-04-17 19:47:29
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原创 【HDLBits刷题】Mux256to1.
Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.Expected solution length: Around 1 line.256选1数据选择器，不用case，不.
2022-04-17 19:30:20
783
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