Sequential---Counters_1

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于 2024-03-29 15:51:52 发布

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文章标签： fpga开发笔记

本文链接：https://blog.youkuaiyun.com/pmlcreating/article/details/137132286

版权

本文详细介绍了四个计数器模块：四比特同步二进制计数器、十进制计数器（包含条件逻辑）、慢速十进制计数器，以及它们的输入输出和时钟控制逻辑。

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1.Four-bit binary counter

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);

    always@(posedge clk)
        begin
            if(reset)
                q<=0;
            else
                begin
                   q<=q+1'b1; 
                end
        end
    
endmodule

2.Decade counter

module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);

    always@(posedge clk)
        begin
            if(reset)
                q<=0;
            else 
                begin
                if(q<4'b1010)
                    q<=q+1'b1;
                if(q==4'b1001)
                    q<=0;
                end
        end
    
endmodule

3.Decade counter again

module top_module (
    input clk,
    input reset,
    output [3:0] q);
    
    always@(posedge clk)
        begin
            if(reset)
                q<=1;
            else
                begin
                    if(q<10)
                        q<=q+1;
                    else
                        q<=1;
                end
                
        end

endmodule

4.Slow decade counter

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);

    always@(posedge clk)
        begin
            if(reset)
                q<=0;
            else
                begin
                    if(slowena==0)
                        q<=q;
                    else
                        begin
                        if(q<10)
                            q<=q+1;
                        if(q==9)
                            q<=0;
                        end
                end
        end
    
endmodule