`timescale 1ns/1ns
module signal_generator(
input clk,
input rst_n,
input [1:0] wave_choise,
output reg [4:0]wave
);
reg [4:0] cnt;
reg flag;
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt <= 0;
else if(wave_choise == 0) begin
cnt <= (cnt == 19) ? 0 : cnt + 1;
end
else
cnt <= 0;
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
flag <= 0;
else if(wave_choise == 2) begin
if(wave == 1)
flag <= 1;
else if(wave == 19)
flag <= 0;
else
flag <= flag;
end
else
flag <= 0;
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
wave <= 0;
else
case(wave_choise)
0:
begin
if(cnt == 9)
wave <= 20;
else if(cnt == 19)
wave <= 0;
else
wave <= wave;
end
1:
begin
wave <= (wave == 20) ? 0 : wave + 1;
end
2:
begin
wave <= (flag == 0) ? wave -1 : wave + 1;
end
default:
wave <= 0;
endcase
end
endmodule
牛客--VL29--信号发生器
最新推荐文章于 2025-11-25 12:11:25 发布
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