牛客--VL28--输入序列不连续的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

	reg [3:0] data_r;
	always@(posedge clk or negedge rst_n) begin
		if(!rst_n)
			data_r <= 4'b0;
		else
			data_r <= (data_valid) ?  {data_r[2:0],data} : data_r;

	end

	always@(posedge clk or negedge rst_n) begin
		if(!rst_n)
			match <= 1'b0;
		else
			match <= (data_valid && {data_r[2:0],data} == 4'b0110);

	end

  
endmodule