Circuits---Sequential logic--------Latches (1)

1.D flip-flop

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    always @(posedge clk)
        begin
           q<=d; 
        end

endmodule

2.D flip-flops

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    
    always@(posedge clk)
        begin
           q<=d; 
        end

endmodule

3.DFF with reset

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);

    always@(posedge clk )
        begin 
            if(!reset)
                q<=d;
            else
                q<=0;
        end
    
endmodule

4.DFF with reset  value

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);

    always@(negedge clk)
        begin
            if(!reset)
                q<=d;
            else
                q<=8'h34;
        end
    
endmodule

5.DFF with asynch reset

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);

    always@(posedge clk or posedge areset)
        begin
            if(areset) // 高电平有效
                q<=0;
            else 
                q<=d;
        end
    
endmodule