Circuits--Combinational--Basic_3

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#fpga开发 #笔记

本文展示了五个Verilog模块实例，包括基本逻辑门组合、状态机控制的铃声/振动器、温控器、3位计数器以及处理更长向量的逻辑操作。这些模块展示了在硬件描述语言中实现简单到复杂功能的基本结构。

1.simple circuit B

module top_module ( input x, input y, output z );
    assign z=~(x^y);
endmodule

2.combine circuits A and B

module top_module (input x, input y, output z);  
    wire z1,z2,z3,z4;
    
    assign z1=~(x^y);
    assign z2=(x^y)&x;
    assign z3=~(x^y);
    assign z4=(x^y)&x;
    
    assign z=(z1|z2)^(z3&z4);

endmodule

3.Ring or vibrate

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,       // Make sound
    output motor         // Vibrate
);

    always@(*)
        begin
            if(ring==1)
                begin
                    if(vibrate_mode) 
                        begin
                            motor=1;
                            ringer=0; 
                        end
                    else
                        begin
                            motor=0; 
                            ringer=1;
                        end
                end
            else
                begin
                    motor=0;
                   ringer=0;
                end
        end
endmodule

4.thermostat

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
    
    assign heater= (mode&too_cold) ? 1:0;
    assign aircon= (~mode&too_hot) ? 1:0;
    assign fan= (heater|aircon|fan_on) ? 1:0;

endmodule

5. 3-bit population count

module top_module( 
    input [2:0] in,
    output [1:0] out );
    
    integer i;
    always@(*)
        begin
            out=0;
            for(i=0;i<3;i++)
                if(in[i])
                    out=out+1;
        end

endmodule

6.Gates and vectors

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
    
    integer i;
    always@(*)
        begin
            for(i=0;i<4;i++)
                begin
                    if(i<3)
                        begin
                            out_both[i]= (in[i]&in[i+1]) ? 1:0;
                            out_any[i+1]= (in[i+1]|in[i]) ? 1:0;
                            out_different[i]= (in[i]^in[i+1]) ? 1:0;
                  
                        end
                    if(i==3)
                        out_different[i]=(in[i]^in[i-3]) ? 1:0;
                end
        end

endmodule

7.Even longer vectors

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );
    
     integer i;
    always@(*)
        begin
            for(i=0;i<100;i++)
                begin
                    if(i<99)
                        begin
                            out_both[i]= (in[i]&in[i+1]) ? 1:0;
                            out_any[i+1]= (in[i+1]|in[i]) ? 1:0;
                            out_different[i]= (in[i]^in[i+1]) ? 1:0;
                  
                        end
                    if(i==99)
                        out_different[99]=(in[99]^in[0]) ? 1:0;
                end
        end

endmodule