Verilog Language-----Basics

simple wire

module top_module( input in, output out );
wire rhs;
    assign rhs = in;
    assign out = rhs;
    
endmodule

Four wires

module top_module( 
    input a,b,c,
    output w,x,y,z );
    wire aw;
    wire bw;
    wire cw;
    assign aw = a;
    assign w = aw;
    
    assign bw = b;
    assign x = bw;
    assign y = bw;
    
    assign cw = c;
    assign z = cw;

endmodule

Inverter

module top_module( input in, output out );
wire rhs;
assign rhs = in;
assign out = ~rhs;
endmodule

AND gate

module top_module( 
    input a, 
    input b, 
    output out );

    assign out=a&b;
endmodule

NOR gate

module top_module( 
    input a, 
    input b, 
    output out );
    
    assign out = ~(a|b);

endmodule

XNOR gate

module top_module( 
    input a, 
    input b, 
    output out );

    assign