设计定义:1.让LED灯按照亮0.25s,灭0.75的状态循环亮灭
一、代码实现
`timescale 1ns / 1ns
module led_step1(
input clk ,
input rstn ,
output led
);
reg[23:0] cnt ;
reg[1:0] count ;
reg r_led ;
assign led = r_led ;
always @(posedge clk or negedge rstn) begin
if(!rstn)
cnt <= 0;
else if(cnt == 12_500_000 - 1)
cnt <= 0;
else
cnt <= cnt + 1'd1;
end
always @(posedge clk or negedge rstn) begin
if(!rstn)
count <= 0;
else if(cnt == 12_500_000 - 1)
count <= count + 1'd1;
end
always @(*) begin
case(count)
2'b00: r_led <= 1;
2'b01: r_led <= 0;
2'b10: r_led <= 0;
2'b11: r_led <= 0;
default: r_led <= 0;
endcase
end
endmodule
二、仿真
`timescale 1ns / 1ns
module led_step1_tb();
reg clk ;
reg rstn ;
wire led ;
led_step1 inst0(
.clk (clk ) ,
.rstn (rstn) ,
.led (led )
);
initial clk = 1;
always #10 clk = ~clk;
initial begin
rstn = 0;
#201;
rstn = 1;
#1000_000_000;
$stop;
end
endmodule