本文提供了2023年加特兰公司数字IC设计笔试题的详细内容，包括11道问答题，涵盖了32位二进制转十六进制、MIPS指令编码、Verilog中的阻塞与非阻塞赋值、时钟同步、状态机实现、时钟分频器设计以及相关约束和测试 bench 编写等知识点。难度适中，适合数字电路设计工程师准备面试使用。
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题目背景
- 笔试时间：2022.07.27
- 应聘岗位：数字电路设计工程师（SoC) - 2023届
- 笔试时长：90min
- 笔试平台：nowcoder牛客网
- 题目类型：问答题（11道）
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文章目录
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- 1 What does the Hexadecimal (hex) code for the following 32-bit binary code?
- 2 The table shows the MIPS instructions.
- 3 What is the difference between blocking and nonblocking assignments?
- 4 What is the output of the codes below?
- 5 Explain setup failure and hold failure to a fipflop.
- 6 How to synchronize signals between 2 clock domains?
- 7 Implement gate level circuit synthesized by the continuous assignment module.
- 8 Write FSM by the following state transition diagram. (input: clk, rstn, dat_i; output: dat_o)
- 9 Write clock divider (4-bit) module (input: ck, rstn, div; output: cIk_ div).
- 10 Write clock constraints for input clock (up to 100MHz) and output clock (up to 50MHz) in Problem 9.
- 11 Write testbench for the clock divider module in Problem 9.
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1 What does the Hexadecimal (hex) code for the following 32-bit binary code?
0011 0011 1101 1110 0000 0001 0110 1000 (bin)= _______ (hex)
2 The table shows the MIPS instructions.
Write the 32-bit binary code for instruction “addi r7, r3, -1”.
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