Verilog练习：HDLBits笔记10

三、Circuits

Combinational logic-Karnaugh Map to Circuit

1、3-variable

Problem Statement：

mplement the circuit described by the Karnaugh map below.

module top_module(
    input a,
    input b,
    input c,
    output out  
);
    assign out = a | b | c;

endmodule

2、4-variable 

Problem Statement：

Implement the circuit described by the Karnaugh map below.