Verilog练习：HDLBits笔记16

最新推荐文章于 2024-03-13 20:09:21 发布

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最新推荐文章于 2024-03-13 20:09:21 发布 · 1k 阅读

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本文详细介绍了数字逻辑电路的几个核心组件的设计，包括具有1000周期的计数器、4位移位寄存器兼向下计数器、1101序列检测器、使能移位寄存器的有限状态机以及完整的定时器。每个组件都用Verilog语言进行了建模，并提供了详细的逻辑操作描述。这些设计涵盖了同步复位、状态转换、计数、序列检测和控制信号的产生等功能，展示了数字系统设计的基础和灵活性。

四、Sequential Logic

Building Larger Circuits

1、Counter with period 1000

Problem Statement：

Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0.

module top_module (
    input clk,
    input reset,
    output [9:0] q
);
    reg[9:0]cnt;
    
    always@(posedge clk)begin
        if(reset)
            cnt <= 10'd0;
        else if(cnt == 10'd999)
            cnt <= 10'd0;
        else
            cnt <= cnt + 10'd1;
    end
    
    assign q = cnt;

endmodule

2、4-bit shift register and down counter

Problem Statement：

Build a four-bit shift register that also acts as a down counter. Data is shifted in most-significant-bit first when shift_ena is 1. The number currently in the shift register is decremented when count_ena is 1. Since the full system doesn't ever use shift_ena and count_ena together, it does not matter what your circuit does if both control inputs are 1 (This mainly means that it doesn't matter which case gets higher priority).

module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output [3:0] q);
    
    always@(posedge clk)begin
        case({shift_ena,count_ena})
        	2'b01 : q <= q - 1'b1;
            2'b10 : q <= {q[2:0],data};
        endcase
    end

endmodule

3、Sequence 1101 recognizer

Problem Statement：

Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Getting stuck in the final state is intended to model going to other states in a bigger FSM that is not yet implemented. We will be extending this FSM in the next few exercises.

module top_module (
    input clk,
    input reset,     
    input data,
    output start_shifting
);
    parameter mon  = 3'd1,
    		  s0   = 3'd2,
    		  s1   = 3'd3,
    		  s2   = 3'd4,
    		  s3   = 3'd5;
    
    reg[2:0]current_state;
    reg[2:0]next_state;
    
    always@(posedge clk)begin
        if(reset)
            current_state <= mon;
        else
            current_state <= next_state;
    end
    
    always@(*)begin
        if(reset)
            next_state <= mon;
        else
            case(current_state)
                mon  : next_state <= data ? s0 : mon;
                s0   : next_state <= data ? s1 : mon;   
                s1   : next_state <= data ? s1 : s2;    
                s2   : next_state <= data ? s3 : mon;