AMBA协议AXI-Lite（AXI-Lite从机代码板级验证）

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前言

  在前一章中我们已经完成了从机接口模板代码的设计；在本篇中，我们将对设计的从机代码进行板级验证；

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一、环境

  验证FPGA选用Xilinx的Zynq 7000，基于Vivado平台进行；
  认证过程将采用软硬协同验证，其中内核为MicroBlaze；

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二、测试IP

  测试IP核将基于模板代码修改：
修改后的逻辑文件：

//AXI Slave interface
module axi_lite_logic#(

	//axi-lite parameter definition start here
	//data width / address width
	parameter integer     C_AXI_SLV_REG_NUM = 8,
	parameter integer     C_AXI_DATA_WIDTH = 32,
	parameter integer     C_AXI_ADDR_WIDTH = $clog2(C_AXI_SLV_REG_NUM*4)+1
	)
(
	output wire   [3:0]                           led,
	input  wire   [3:0]                           key,
	//system signals definition
	input  wire  						 	      s_axi_aclk,
	input  wire  						 	  s_axi_aresentn,  
	//write address signals definition	  
	input  wire [C_AXI_ADDR_WIDTH - 1:0] 	    s_axi_awaddr,
	input  wire                          	   s_axi_awvalid,
	output wire                          	   s_axi_awready,
	//write data signals definition
	input  wire [C_AXI_DATA_WIDTH - 1:0]   		 s_axi_wdata,
	input  wire                            		s_axi_wvalid,
	output wire                            		s_axi_wready,   
	input  wire [(C_AXI_DATA_WIDTH/8) - 1:0]	 s_axi_wstrb,
	//write response signals definition
	output wire [1:0]                            s_axi_bresp,
	output wire                                 s_axi_bvalid,
	input  wire                                 s_axi_bready,
	//read address signals definition
	input  wire [C_AXI_ADDR_WIDTH - 1:0] 	     s_axi_araddr,
	input  wire                         	    s_axi_arvalid,
	output wire                                 s_axi_arready,
	//read data signals definition
	output wire [C_AXI_DATA_WIDTH - 1:0]   		 s_axi_rdata,
	output wire                            		s_axi_rvalid,
	input  wire                                 s_axi_rready,
	//read response signals definition
	output wire                                  s_axi_rresp,
	//protect signals definition
	input  wire                                 s_axi_arprot
);

	localparam integer     ADDR_SHIFT = C_AXI_DATA_WIDTH/16;


	reg [C_AXI_ADDR_WIDTH - 1:0]    axi_awaddr;
	reg                            axi_awready;
	reg							    axi_wready;
	reg [1:0]                        axi_bresp;
	reg                             axi_bvalid;
	reg                                  aw_en;
	reg [C_AXI_ADDR_WIDTH - 1:0]    axi_araddr;
	reg                            axi_arready;
	reg                             axi_rvalid;
	reg [C_AXI_DATA_WIDTH - 1:0]	 axi_rdata;
    reg [C_AXI_DATA_WIDTH - 1:0]  reg_data_out;


	wire                        register_wr_en;

	//register definition
	reg [(C_AXI_DATA_WIDTH - 1) : 0]  slv_reg[0:(C_AXI_SLV_REG_NUM-1)];

	assign led = slv_reg[0][3:0];

    //inner logic definition
    assign register_wr_en = axi_wready & s_axi_wvalid & axi_awready & s_axi_awvalid; 

    //inner signal connect
    assign s_axi_awready = axi_awready;
    assign s_axi_wready = axi_wready;
    assign s_axi_bresp = axi_bresp;
    assign s_axi_bvalid = axi_bvalid;
    assign s_axi_arready = axi_arready;
    assign s_axi_rdata = axi_rdata;
    assign s_axi_rvalid = axi_rvalid;
    assign s_axi_rresp = 2'b00;

	//---------------------------write address input logic--------------------------------//
	//transmit finish whe s_axi_awvalid=1 axi_awready = 1 s_axi_wvalid = 1
	always @(posedge s_axi_aclk) begin : address_input_proc_
		if(~s_axi_aresentn) begin
			axi_awaddr <= 'b0;
			axi_awready <= 1'b0;
			aw_en <= 1'b1;
		end 
		else begin
			if(aw_en && s_axi_awvalid && (~axi_awready) && (s_axi_wvalid))
			begin
				aw_en <= 1'b0;
			 	axi_awaddr <