组合逻辑电路-basic gates

wire：

Implement the following circuit:

                                          

module top_module (
    input in,
    output out);
assign out=in;
endmodule

gnd：

Implement the following circuit:

.                                                    

module top_module (
    output out);
    assign out=1'b0;
endmodule

NOR:

Implement the following circuit:

                                               

module top_module (
    input in1,
    input in2,
    output out);
    assign out=~(in1|in2);
endmodule

another gate:

Implement the following circuit

---

                                                  

module top_module (
    input in1,
    input in2,
    output out);
    assign out=in1&(~in2);
endmodule

two gates:

Implement the following circuit: