Verilog练习：HDLBits笔记7

三、Circuits

Combinational logic-Basic Gates

1、Wire

Problem Statement：

mplement the following circuit:

module top_module (
    input  in,
    output out
);
    assign out = in;

endmodule

 2、GND

Problem Statement：

Implement the following circuit:

module top_module (
    output out
);
    assign out = 1'b0;

endmodule

 3、NOR

Problem Statement：

Implement the following circuit:

module top_module (
    input  in1,
    input  in2,
    output out
);
    assign out = ~(in1 | in2);

endmodule

 4、Another gate

Problem Statement：

Implement the following circuit:

module top_module (
    input in1,
    input in2,
    output out
);
    assign out = ~in2 & in1;

endmodule

 5、Two gates

Problem Statement：

mplement the following circuit:

module top_module (
    input in1,
    input in2,
    input in3,
    output out
);
    wire out1;
    
    assign out1 = ~(in1 ^ in2);
    assign out = out1 ^ in3;

endmodule

  6、More logic gates

Problem Statement：

Build a combinational circuit with two inputs, a and b.

There are 7 outputs, each with a logic gate