HDLBits刷题Latches and Flip-Flops合集

最新推荐文章于 2023-06-13 10:19:52 发布

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最新推荐文章于 2023-06-13 10:19:52 发布

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本文档详细介绍了不同类型的触发器，如D Flip-Flop、带复位和下降沿触发的触发器、异步清零D触发器等，并通过实例展示它们的实现与工作原理。涵盖了同步与异步操作，适用于时序逻辑设计的基础理解。

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D flip-flop触发器

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments

    always @(posedge clk)
        begin
           q<=d; 
        end
endmodule

Dff8r带复位的触发器

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk)
        begin
            if(reset)
                begin
                    q<=0;
                end
           else
               q<=d;
        end
endmodule

Dff8p下降沿触发带复位的触发器

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    always @(negedge clk)
        begin
            if(reset)
                begin
                    q<=8'h34;
                end
           else
               q<=d;
        end
endmodule

Dff8ar异步清零端的D触发器

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk or posedge areset)  //注意和同步的区别
        begin
            if(areset)
                begin
                    q<=8'h0;
                end
           else
               q<=d;
        end
endmodule

Exams/m2014 q4a D触发器

module top_module (
    input d, 
    input ena,
    output q);

    always @(*)
    begin
        if(ena)
        q <= d;  
    end
endmodule

Exams/m2014 q4b

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);

    always @(posedge clk or posedge ar)
        begin
            if(ar)
                q <= 0;
            else
                begin
                    q <= d;
                end
        end
    
endmodule

Exams/m2014 q4c

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);

    always @(posedge clk)
    begin
        if(r)
            q <= 0;
        else
            q <= d;
    end
endmodule

Exams/m2014 q4d

module top_module (
    input clk,
    input in, 
    output out);

    always @(posedge clk)
        begin
           out <=  in^out;
        end
    
endmodule

Mt2015 muxdff

没看懂题目

Exams/2014 q4a

没看懂题目

Exams/ece241 2014 q4

module top_module (
    input clk,
    input x,
    output z
); 

    reg q0=0,q1=0,q2=0;
    always @(posedge clk)
        begin
            q0 <= x^q0;
        end
    always @(posedge clk)
        begin
            q1 <= x&~q1;
        end
    always @(posedge clk)
        begin
            q2 <= x|~q2;
        end
    assign z = ~(q0 | q1 | q2);
endmodule

Exams/ece241 2013 q7

module top_module (
    input clk,
    input j,
    input k,
    output Q); 

    always @(posedge clk)
    begin
        if(j^k)
            begin
                if(j)
                    Q = 1;
                else
                Q = 0;
            end
        else
            begin
                if(j==1&k==1)
                    Q = ~Q;                   
            end
    end
endmodule

Edgedetect

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);

    reg [7:0]in_old;
    always @(posedge clk)
        begin
            in_old <= in;
            pedge = in&~in_old;
        end
    
endmodule

Edgedetect2

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);

    reg [7:0]in_old;
    always @(posedge clk)
        begin
           in_old <= in;
           anyedge <= in^in_old;
        end
endmodule

Edgecapture

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);

    reg [31:0]in_old;
    always @(posedge clk)
        begin
            in_old <= in;
            if(reset)
                out = 0;
            else
                begin
            
            out <= out|~in&in_old;
                end
        end
        
        
    
endmodule