这篇博客详细记录了各种逻辑门的实现，包括非门、与门、或非门、异或非门等基本逻辑操作。进一步，讨论了线声明、7458芯片的应用、向量的部分赋值和连接，以及加法器、触发器的设计。还涵盖了模块的调用、条件语句、归约运算符和卡诺图在组合逻辑和时序逻辑设计中的应用。
非门
module top_module( input in, output out );
assign out=~in;
endmodule
andgate与门
module top_module(
input a,
input b,
output out );
assign out=a&&b;
endmodule
norgate或非门
module top_module(
input a,
input b,
output out );
assign out=~(a||b);
endmodule
xnorgate异或非门
module top_module(
input a,
input b,
output out );
assign out = ~(a^b);
endmodule
Wire decl
`default_nettype none
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n );
wire x,y,z;
assign x = a&&b,
y = c&&d,
z = x||y,
out = z,
out_n = ~z;
endmodule
7458
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p2y = (p2a&&p2b)||(p2c&&p2d),
p1y = (p1a&&p1c&&p1b)||(p1f&&p1e&&p1d);
endmodule
vector0部分赋值
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0 ); // Module body starts after module declaration
assign
outv = vec,
o0 = outv [0],
o1 = outv [1],
o2 = outv [2];
// This is ok too: assign {o2, o1, o0} = vec;
endmodule
vector1部分赋值
`default_nettype none // Disable implicit nets. Reduces some types of bugs.
module top_module(
input wire [15:0] in,
output wire [7:0] out_hi,
output wire [7:0] out_lo );
assign
out_hi = in[15:8],
out_lo = in[7:0];
endmodule
Vector2部分赋值
module top_module(
input [31:0] in,
output [31:0] out );//
// assign out[31:24] = ...;
assign
out[31:24] = in[ 7: 0],
out[23:16] = in[15: 8],
out[15: 8] = in[23:16],
out[ 7: 0] = in[31:24];
endmodule
Vectorgates(归约运算符运算符和逻辑运算符)
module top_module(
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign
out_or_bitwise = a|b,
out_or_logical = a||b,
out_not[5:3] = ~b,
out_not[2:0] = ~a;
endmodule
Gates4按位操作符
module top_module(
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign
out_and = &in,
out_or = |in,
out_xor = ^in;
endmodule
Vector3连接运算符{}
module top_module (
input [4:0] a, b, c, d, e, f,
output [7:0] w, x, y, z );//
// assign { ... } = { ... };
assign
w = {a[4:0],b[4:2]},
x = {b[1:0],c[4:0],d[4:4]},
y = {d[3:0],e[4:1]},
z = {e[0:0],f[4:0],2'b11};
//{w[7:0], x[7:0], y[7:0], z[7:0]} = {a[4:0], b[4:0], c[4:0], d[4:0]};
endmodule
Vectorr倒置输出
module top_module(
input [7:0] in,
output [7:0] out
);
assign
out[7:0] = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
endmodule
Vector4复制运算符{{}}
module top_module (
input [7:0] in,
output [31:0] out );//
// assign out = { replicate-sign-bit , the-input };
assign out = {{24{in[7]}},in};
endmodule
Vector5
module top_module (
input a, b, c, d, e,
output [24:0] out );//
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
assign out = ~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}}^{5{a,b,c,d,e}};
endmodule
Module模块调用
module top_module ( input a, input b, output out );
mod_a U1(.in1(a),.in2(b),.out(out)); //端口名对应方式
//mod_a U1(a,b,out); 端口位置对应方式
endmodule
Module pos(同上，端口位置对应)
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a U1(out1,out2,a,b,c,d);
endmodule
Module name(同上，端口名对应)
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a U1(
.out1(out1),
.out2(out2),
.in1(a),
.in2(b),
.in3(c),
.in4(d)
);
endmodule
Module shift移位器
module top_module ( input clk, input d, output q );
wire q1,q2;
my_dff U1(clk,d,q1);
my_dff U2(clk,q1,q2);
my_dff U3(clk,q2,q);
endmodule
Module shift8(同上)
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output [7:0] q
);
wire [7:0] q1;
wire [7:0] q2;
wire [7:0] q3;
//wire [7:0] o1, o2, o3;
my_dff8 D1(clk,d,q1);
my_dff8 D2(clk,q1,q2);
my_dff8 D3(clk,q2,q3);
always @(sel or d or q1 or q2 or q3)
case(sel)
2'b00: q = d;
2'b01: q = q1;
2'b10: q = q2;
default:q = q3;
endcase
endmodule
Module add(16-32位加器)
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire c,d;
wire [15:0]sum1,sum2;
add16 A1(a[15:0],b[15:0],1'b0,sum1,c);
add16 A2(a[31:16],b[31:16],c,sum2,d);
assign sum = {sum2[15:0],sum1[15:0]};
endmodule
Module fadd(全加器)
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);//
wire [15:0]sum0,sum1;
wire cout0,cout1;
add16 A0(a[15:0],b[15:0],1'b0,sum0,cout0);
add16 A1(a[31:16],b[31:16],cout0,sum1,cout1);
assign
sum = {sum1,sum0};
endmodule
module add1 ( input a,
input b,
input cin,
output sum,
output cout );
assign
sum = a^b^cin,
cout = a&b|a&cin|b&cin;
// Full adder module here
endmodule
Module cseladd进位选择加法器
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire [15:0]sum0,sum1,sum2;
wire cout0,cout1,cout2;
add16 A0(a[31:16],b[31:16],1'b0,sum0,cout0);
add16 A1(a[31:16],b[31:16],1'b1,sum1,cout1);
add16 A2(a[15:0],b[15:0],1'b0,sum2,cout2);
always @(*)
case(cout2)
1'b0: sum = {sum0,sum2};
default sum = {sum1,sum2};
endcase
endmodule
Module addsub加减法器（补码）
module top_module(
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire [15:0]sum0,sum1;
wire cout0,cout1;
wire [31:0]c = {32{sub}}^b;
add16 A0(a[15:0],c[15:0],sub,sum0,cout0);
add16 A1(a[31:16],c[31:16],cout0,sum1,cout1);
assign sum = {sum1,sum0};
endmodule
Alwaysblock1
- Combinational: always @(*)
- Clocked: always @(posedge clk)
// synthesis verilog_input_version verilog_2001
module top_module(
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a&b;
always @(*)
out_alwaysblock = a&b;
endmodule
Alwaysblock2
- Combinational: always @(*) 用阻塞赋值
- Clocked: always @(posedge clk) 用非阻塞赋值
// synthesis verilog_input_version verilog_2001
module top_module(
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb = a^b,
output reg out_always_ff );
assign out_assign = a^b;
always @(*)
out_always_comb = a^b;
always @(posedge clk)
out_always_ff = a^b;
endmodule
Always if二选一数字选择器
// synthesis verilog_input_version verilog_2001
module top_module(
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always );
always @(*)
if(sel_b1&sel_b2)
out_always = b;
else
out_always = a;
assign out_assign = (sel_b1&sel_b2)?b:a;
endmodule
Always if2
// synthesis verilog_input_version verilog_2001
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving ); //
always @(*) begin
if (cpu_overheated)
shut_off_computer = 1;
else
shut_off_computer = 0;
end
always @(*) begin
if (~arrived)
keep_driving = ~gas_tank_empty;
else
keep_driving = 0;
end
endmodule
Always case
// synthesis verilog_input_version verilog_2001
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out );//
always@(*)
begin // This is a combinational circuit
case(sel)
3'b000: out = data0;
3'b001: out = data1;
3'b010: out = data2;
3'b011: out = data3;
3'b100: out = data4;
3'b101: out = data5;
default: out = 0;
endcase
end
endmodule
Always case2
// synthesis verilog_input_version verilog_2001
module top_module (
input [3:0] in,
output reg [1:0] pos );
always @(*)
begin
casez(in)
4'bzzz1: pos = 2'd0;
4'bzz1z: pos = 2'd1;
4'bz1zz: pos = 2'd2;
4'b1zzz: pos = 2'd3;
default:pos = 2'd0;
endcase
end
endmodule
Always casez
// synthesis verilog_input_version verilog_2001
module top_module (
input [7:0] in,
output reg [2:0] pos );
always @(*) begin
casez (in)
8'bzzzzzzz1: pos = 3'd0;
8'bzzzzzz1z: pos = 3'd1;
8'bzzzzz1zz: pos = 3'd2;
8'bzzzz1zzz: pos = 3'd3;
8'bzzz1zzzz: pos = 3'd4;
8'bzz1zzzzz: pos = 3'd5;
8'bz1zzzzzz: pos = 3'd6;
8'b1zzzzzzz: pos = 3'd7;
default: pos = 0;
endcase
end
endmodule
Always nolatches避免门闩
// synthesis verilog_input_version verilog_2001
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up );
always @(*)
begin
case(scancode)
16'he06b:
begin
left = 1;
right = 0;
up = 0;
down = 0;
end
16'he072:
begin
left = 0;
right = 0;
up = 0;
down = 1;
end
16'he074:
begin
left = 0;
right = 1;
up = 0;
down = 0;
end
16'he075:
begin
left = 0;
right = 0;
up = 1;
down = 0;
end
default:
begin
left = 0;
right = 0;
up = 0;
down = 0;
end
endcase
end
endmodule
Conditional三目运算符
module top_module (
input [7:0] a, b, c, d,
output [7:0] min);//
// assign intermediate_result1 = compare? true: false;
wire [7:0]min1,min2;
assign
min1=(a<b)?a:b,
min2=(c<d)?c:d,
min=(min1<min2)?min1:min2;
endmodule
Reduction归约运算符（奇偶校验器）逐位异或
module top_module (
input [7:0] in,
output parity);
assign parity = ^in;
endmodule
Gates100
module top_module(
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
assign
out_and = &in,
out_or = |in,
out_xor = ^in;
endmodule
Vector100r（for循环）
module top_module(
input [99:0] in,
output [99:0] out
);
always@(*)begin
for (int i=0;i<=99;i=i+1)
begin
out[i]=in[99-i];
end
end
endmodule
Popcount255
module top_module(
input [254:0] in,
output [7:0] out );
always @(*)
begin
out = 0;
for(int i=0;i<=254;i=i+1)
begin
if(in[i])
out = out + 1;
end
end
endmodule
Mt2015 eq2
module top_module ( input [1:0] A, input [1:0] B, output z );
always @(*)
begin
if(A == B)
z = 1;
else
z = 0;
end
//assign z = (A[1:0]==B[1:0]);
endmodule
Mt2015 q4a
module top_module (input x, input y, output z);
assign z = (x^y) & x;
endmodule
Mt2015 q4b
module top_module ( input x, input y, output z );
assign z = ~(x^y);
endmodule
Mt2015 q4
module top_module (input x, input y, output z);
wire z1,z2;
assign
z1 = x^y & x,
z2 = ~(x^y),
z = (z1 | z2)^(z1 & z2);
endmodule
Ringer
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign
ringer = (ring==1 & vibrate_mode==0 )? 1:0,
motor = (ring==1 & vibrate_mode== 1)?1:0;
endmodule
Thermostat
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign
heater = too_cold & mode,
aircon = too_hot & ~mode,
fan = (too_cold & mode | too_hot & ~mode)|fan_on ;
endmodule
Popcount3
module top_module(
input [2:0] in,
output [1:0] out );
always @(*)
begin
out = 2'b0;
for(integer i=0;i<3;i++)
if(in[i])
begin
out = out+1;
end
end
endmodule
Gatesv
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
assign
out_both = {in[2]&in[3],in[1]&in[2],in[0]&in[1]}, //out_both = in[2:0] & in[3:1]
out_any = {in[3]|in[2],in[2]|in[1],in[1]|in[0]}, //out_any = in[3:1] | in[2:0]
out_different = {in[3]^in[0],in[2]^in[3],in[1]^in[2],in[0]^in[1]};
//out_different = in ^ {in[0], in[3:1]}
endmodule
Gatesv100
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
assign
out_both = in[98:0] & in[99:1],
out_any = in[99:1] | in[98:0],
out_different = in ^ {in[0],in[99:1]};
endmodule
Mux2to1
module top_module(
input a, b, sel,
output out );
assign out = (sel?b:a);
endmodule
Mux2to1v
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
assign out = (sel?b:a);
endmodule
Mux9to1v
module top_module(
input [15:0] a, b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
always @(*)
begin
case(sel)
4'd0:out=a;
4'd1:out=b;
4'd2:out=c;
4'd3:out=d;
4'd4:out=e;
4'd5:out=f;
4'd6:out=g;
4'd7:out=h;
4'd8:out=i;
default:out=16'hffff;
endcase
end
endmodule
Mux256to1
module top_module(
input [255:0] in,
input [7:0] sel,
output out );
assign out = in[sel];
endmodule
Mux256to1v
module top_module(
input [1023:0] in,
input [7:0] sel,
output [3:0] out );
assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};
endmodule
Hadd
module top_module(
input a, b,
output cout, sum );
assign
cout = a&b,
sum = a^b;
endmodule
Fadd
module top_module(
input a, b, cin,
output cout, sum );
assign
sum = a^b^cin,
cout = a&b | a&cin | b&cin;
endmodule
Adder3
module top_module(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
add1 a0(
.a(a[0]),
.b(b[0]),
.cin(cin),
.cout(cout[0]),
.sum(sum[0]));
add1 a1(
.a(a[1]),
.b(b[1]),
.cin(cout[0]),
.cout(cout[1]),
.sum(sum[1]));
add1 a2(
.a(a[2]),
.b(b[2]),
.cin(cout[1]),
.cout(cout[2]),
.sum(sum[2]));
endmodule
module add1(
input a, b, cin,
output cout, sum );
assign
sum = a^b^cin,
cout = a&b | a&cin | b&cin;
endmodule
Exams/m2014 q4j
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum);
wire [3:0] cout;
add1 a0(
.a(x[0]),
.b(y[0]),
.cin(0),
.cout(cout[0]),
.sum(sum[0]));
add1 a1(
.a(x[1]),
.b(y[1]),
.cin(cout[0]),
.cout(cout[1]),
.sum(sum[1])); //全部代码等价于assign sum = a+b+cin;
add1 a2(
.a(x[2]),
.b(y[2]),
.cin(cout[1]),
.cout(cout[2]),
.sum(sum[2]));
add1 a3(
.a(x[3]),
.b(y[3]),
.cin(cout[2]),
.cout(cout[3]),
.sum(sum[3]));
assign sum[4] = cout[3];
endmodule
module add1(
input a, b, cin,
output cout, sum );
assign
sum = a^b^cin,
cout = a&b | a&cin | b&cin;
endmodule
Adder100
module top_module(
input [99:0] a, b,
input cin,
output cout,
output [99:0] sum );
assign {cout,sum} = a+b+cin;
endmodule
Bcdadd4
module top_module (
input [15:0] a, b,
input cin,
output cout,
output [15:0] sum );
wire [3:0] cout1;
bcd_fadd U0(
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(cout1[0]));
genvar i;
generate
for(i=1;i<4;i++)
begin:add_16
bcd_fadd U1(
.a(a[4*i+3:4*i]),
.b(b[4*i+3:4*i]),
.cin(cout1[i-1]),
.sum(sum[4*i+3:4*i]),
.cout(cout1[i]));
end
endgenerate
assign cout = cout1[3];
endmodule
Kmap1卡诺图
module top_module(
input a,
input b,
input c,
output out );
assign out = a|b|c; //注意不要写成a+b+c；
endmodule
Kmap2
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ((~a)|(~b)|c)&((~b)|c|(~d))&(a|b|(~c)|(~d))&((~a)|(~c)|d);
endmodule
Kmap3
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = a|~b&c;
endmodule
Kmap4
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ~a&b&~c&~d | a&~b&~c&~d |~a&~b&~c&d |a&b&~c&d | ~a&b&c&d | a&~b&c&d | ~a&~b&c&~d |a&b&c&~d;
endmodule
Exams/ece241 2013 q2
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign
out_sop = c&d|c&~a&~b,
out_pos = ~((~c|~d)&(~c|a|b));
endmodule
Exams/m2014 q3
module top_module (
input [4:1] x,
output f );
assign f = ~x[1]&x[3]|x[1]&x[2]&~x[3];
endmodule
Exams/2012 q1g
module top_module (
input [4:1] x,
output f
);
assign f = ~x[1]&x[3]|x[2]&x[3]&x[4]|x[1]&~x[2]&~x[4]|~x[2]&~x[3]&~x[4];
endmodule
Dff触发器
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q );//
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
always @(posedge clk)
begin
q<=d;
end
endmodule
Dff8
同上
Dff8r带复位的触发器
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk)
begin
if(reset)
begin
q<=0;
end
else
q<=d;
end
endmodule
Dff8p下降沿触发带复位的触发器
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @(negedge clk)
begin
if(reset)
begin
q<=8'h34;
end
else
q<=d;
end
endmodule
Dff8ar异步清零端的D触发器
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk or posedge areset)
begin
if(areset)
begin
q<=8'h0;
end
else
q<=d;
end
endmodule
Dff16e带使能位的16位触发器
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always @(posedge clk)
begin
if(~resetn)
q<=0;
else //注意if和else之间的关系
begin
if(byteena[1])
q[15:8]<=d[15:8];
if(byteena[0]) //这里不能用else if
q[7:0]<=d[7:0];
end
end
endmodule
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