FPGA学习verilog基础语法练习实现取最大值

verilog基础语法练习

设计目标：设计输入4个8位的变量，输出最大值模块

框图

代码

opra文件

module opre (
    input wire [7:0]A,
    input wire [7:0]B,
    input wire [7:0]C,
    input wire [7:0]D,
    output wire [7:0]Y
);

assign Y = (A>B&&A>C&&A>D)?A:
           (B>A&&B>C&&B>D)?B:
           (C>A&&C>B&&C>D)?C:
           (D>A&&D>B&&D>C)?D:
           8'b00000000;
    
endmodule

tb文件

`timescale 1ns/1ps

module opre_tb ();


reg [7:0]A;
reg [7:0]B;
reg [7:0]C;
reg [7:0]D;
wire [7:0]Y;

initial begin
    A =  8'b00000000;
    B =  8'b00000000;
    C =  8'b00000000;
    D =  8'b00000000;
end


always #2 A = {$random} % 256;
always #2 B = {$random} % 256;
always #2 C = {$random} % 256;
always #2 D = {$random} % 256;

opre opre_1(
    .A(A),
    .B(B),
    .C(C),
    .D(D),
    .Y(Y)
);

endmodule

仿真结果