牛客网--VL73 串行进位加法器

`timescale 1ns/1ns

module add_4(
   input         [3:0]  A   ,
   input         [3:0]  B   ,
   input                Ci  , 

   output	wire [3:0]  S   ,
   output   wire        Co   
);


wire s1;
wire s2;
wire s3;
wire s4;

wire c1;
wire c2;
wire c3;
wire c4;


add_full f1(
    .A(A[0]),
    .B(B[0]),
    .Ci(Ci),
    .S(s1),
    .Co(c1)
);

add_full f2(
    .A(A[1]),
    .B(B[1]),
    .Ci(c1),
    .S(s2),
    .Co(c2)
);

add_full f3(
    .A(A[2]),
    .B(B[2]),
    .Ci(c2),
    .S(s3),
    .Co(c3)
);

add_full f4(
    .A(A[3]),
    .B(B[3]),
    .Ci(c3),
    .S(s4),
    .Co(c4)
);

assign Co = c4;
assign S[0] = s1;
assign S[1] = s2;
assign S[2] = s3;
assign S[3] = s4;



endmodule


module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);

wire c_1;
wire c_2;
wire sum_1;

add_half add_half_1(
   .A   (A),
   .B   (B),
         
   .S   (sum_1),
   .C   (c_1)  
);
add_half add_half_2(
   .A   (sum_1),
   .B   (Ci),
         
   .S   (S),
   .C   (c_2)  
);

assign Co = c_1 | c_2;
endmodule