Formal -- VC Formal FPV study

Introduction to Formal Verification

Requirements

• Assertion/Cover
• Assume(Constraint)
• Synthesizable RTL

Formal Results

• Proof
• Falsification
• Bounded Proof

VC Formal

Flow

Components

FPV

Methodology

Inputs for FPV

Analyze and elaborate commands (example, read_file )

Clock and reset commands (example, create_clock, create_reset )

Execute commands (example, check_fv )

Report commands (example, report_fv )

 Onputs for FPV

Property Status

• Assertion status: Proven, Falsified, Vacuous(先决条件没有cover到), Witness-Coverable, Uncoverable and Inconclusive(没有得到证明)
• Assume status: Non-Vacuous, Vacuous(assume无效),Uncoverable and Inconclusive
• Cover status: Coverable and Uncoverable

Execue FPV

vcf -f run.tcl

vcf -f run.tcl -verdi

 Analyzing Results

report_fv

Property Control

Formal Runtime Control

控制time/memory/engine

• set_fml_var fml_max_time <time, ex. 24H>
• set_fml_var fml_progress_time_limit <time, ex. 100M>
• set_fml_var fml_max_mem <Maximum memory size>

Controlling Engine Effort

• set_engine [-on|-off] <engine id>
• set_fml_var fml_effort <effort level, ex. high>

Controlling Resume

• set_fml_var fml_enable_resume true
• set_fml_var fml_enable_resume_depth true

Controlling Grid Usage

• set_grid_usage -type [LSF|SGE|RTDA]=<#_of_workers> ...
• report_grid_usage

Convergence Improvement

• snip_driver
• set_blackbox
• set_abstractions
• get_abstractions
• report_abstraction

sni