IMPL10. formality 常用变量浅析

1.hdlin_unresolved_modules //hdlin_xxx

控制对于link的时候，对于找不到ref的instance，处理方法；当设置为error或者默认值时会报告link的error，当设置为blackbox时会对找不到ref的instance默认设置为blackbox；

注意：hdlin_xxx这一类的变量设置；

NAME

hdlin_unresolved_modules

Specifies how to control black box creation for unresolved design references.

TYPE

string

DEFAULT

"error"

DESCRIPTION

Use this variable to control black box creation for Verilog or VHDL descriptions of references that are not resolved during set_top.

To change the value of this variable, enter set hdlin_unresolved_modules "value", where value is "black_box" or "error".

* "black_box" - Your unresolved Verilog and VHDL design references are turned into black boxes.

* "error" - Unresolved Verilog and VHDL design references are treated as errors.