通用的双向IO的VERILOG实现

1，编译通过。

2，需要编写驱动。

module wb_io
#(parameter CH_WIDTH=16)(
 input clk,
 input wb_rd ,wb_wr,
 input rst,
 input [1:0]wb_addr,
 input [31:0]wb_din,
 output reg [31:0]wb_dout,
 inout [CH_WIDTH-1:0]io 
 );
 
reg [CH_WIDTH-1:0]oen;
reg [CH_WIDTH-1:0]d_out;


always @ (posedge clk)
if (wb_wr) case (wb_addr[1:0])
0:d_out[CH_WIDTH-1:0]<=wb_din[CH_WIDTH-1:0];
1:oen[CH_WIDTH-1:0]<=wb_din[CH_WIDTH-1:0];
endcase 


always @ (posedge clk)
wb_dout[CH_WIDTH-1:0]<=io[CH_WIDTH-1:0];
 
    genvar i;
    generate
        for(i=0;i<CH_WIDTH;i=i+1)
        begin : gen16
assign  io[i] = (oen[i])?d_out[i] :1'bz;     
    end        
    endgenerate

endmodule