时序逻辑的测试模块

1.新建文件夹命名p2s
2新建一个工程，点击输入框，输入代码
module p2s(data_in,clock,reset,load,data_out,done);
input [3:0] data_in;
input clock,reset, load;
output data_out;
output done;
reg done;
reg [3:0] temp;
reg [3:0] cnt;
always@(posedge clock or posedge reset )
begin
if(reset)
begin
temp<=0;
cnt<=0;
done<=1;
end
else if(load)
begin
temp<=data_in;
cnt<=0;
done<=0;
end
else if(cnt3)
begin
temp <={temp[2:0],1’b0};
cnt<=0;
done<=1;
end
else
begin
temp <= {temp[2:0],1’b0};
cnt<=cnt+1;
done<=0;
end
end
assign data_out=(done1)?1’bz:temp[3];
endmodule

3.点击运行按钮，开始运行检查错

4.全部正确后，改变仿真途径为modelsim开始进行联合仿真

5.改变波长数值导出结果

6.视频链接：https://www.bilibili.com/video/BV1cU4y1j7Jj?share_source=copy_web