Verilog练习：HDLBits笔记13

四、Sequential Logic 

Shift Registers

1、4-bit shift register

Problem Statement：

Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.

• areset: Resets shift register to zero.
• load: Loads shift register with data[3:0] instead of shifting.
• ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears).
• q: The contents of the shift register.

If both the load and ena inputs are asserted (1), the load input has higher priority.

module top_module(
    input clk,
    input areset,  
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q
); 
    always@(posedge clk or posedge areset)begin
        if(areset)
            q <= 4'd0;
        else if(load)
            q <= data;
        else if(ena)
            q <= q >> 1;
        else
            q <= q;
    end

endmodule

2、Left/right rotator

Problem Statement：

Build a 100-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rotates the bits around and does not modify/discard them.

• load: Loads shift register with data[99:0] instead of rotating.
• ena[1:0]: Chooses whether and which direction to rotate.
  • 2'b01 rotates right by one bit
  • 2'b10 rotates left by one bit
  • 2'b00 and 2'b11 do not rotate.
• q: The contents of the rotator.

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q
); 
    always@(posedge clk)begin
        if(load)
            q <= data;
        else if(ena[0] ^ ena[1])
            if(ena[0] == 0)
                q <= {q[98:0],q[99]};
        	else
                q <= {q[0],q[99:1]}; 
        else 
            q <= q;    
    end

endmodule

3、Left