Verilog练习：HDLBits笔记2

二、Verilog Language

Basics

1、Simple wire

Problem Statement：

Create a module with one input and one output that behaves like a wire.

module top_module( 
    input  in, 
    output out 
);
assign out = in;
endmodule

2、four wires

Problem Statement：

Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections: 

a -> w
b -> x
b -> y
c -> z

module top_module( 
    input a,b,c,
    output w,x,y,z 
);
assign w = a;
assign x = b;
assign x = b;
assign z = c;
endmodule

3、Inverter 

Problem Statement：

Create a module that implements a NOT gate.

module top_module( 
    input in, 
    output out 
);
assign out = ~in;
endmodule

 4、AND