VerilogHDL学习-Module shift8-HDLBits

原创

已于 2023-04-08 08:48:02 修改 · 308 阅读

0 ·

CC 4.0 BY-SA版权

文章标签：

#学习 #fpga开发

于 2022-05-06 10:07:51 首次发布

本篇博客介绍如何使用Verilog设计一个包含8位D触发器的移位寄存器，并通过实例展示了如何将3个这样的模块级联形成一个8位宽、长度为3的移位寄存器。同时，还构建了一个4选1多路选择器，根据输入信号选择从零到三个时钟周期延迟后的输入信号输出。

This exercise is an extension of module_shift. Instead of module ports being only single pins, we now have modules with vectors as ports, to which you will attach wire vectors instead of plain wires. Like everywhere else in Verilog, the vector length of the port does not have to match the wire connecting to it, but this will cause zero-padding or trucation of the vector. This exercise does not use connections with mismatched vector lengths.

You are given a module with two inputs and one output (that implements a set of 8 D flip-flops). Instantiate three of them, then chain them together to make a 8-bit wide shift register of length 3. In addition, create a 4-to-1 multiplexer (not provided) that chooses w