VerilogHDL学习-Module shift8-HDLBits

This exercise is an extension of module_shift. Instead of module ports being only single pins, we now have modules with vectors as ports, to which you will attach wire vectors instead of plain wires. Like everywhere else in Verilog, the vector length of the port does not have to match the wire connecting to it, but this will cause zero-padding or trucation of the vector. This exercise does not use connections with mismatched vector lengths.

You are given a module with two inputs and one output (that implements a set of 8 D flip-flops). Instantiate three of them, then chain them together to make a 8-bit wide shift register of length 3. In addition, create a 4-to-1 multiplexer (not provided) that chooses what to output depending on : The value at the input d, after the first, after the second, or after the third D flip-flop. (Essentially, selects how many cycles to delay the input, from zero to three clock cycles.) my_dff8sel[1:0]sel

The module provided to you is: module my_dff8 ( input clk, input [7:0] d, output [7:0] q );

The multiplexer is not provided. One possible way to write one is inside an block with a statement inside.

自己参考书籍给出的结果：

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    wire[7:0] wire1,wire2,wire3;
    my_dff8 a1(clk,d,wire1);
    my_dff8 a2(clk,wire1,wire2);
    my_dff8 a3(clk,wire2,wire3);
    always@(sel,d,wire1,wire2,wire3,clk)
        begin
        case(sel)
            2'b00:q=d;
            2'b01:q=wire1;
            2'b10:q=wire2;
            2'b11:q=wire3;
            default:q=7'bx;
        endcase
        end
endmodule