FPGA project： led

 

module led(
    input           key_in      ,

    output          led_out     
);

    assign led_out = key_in ;
    
endmodule

`timescale 1ps/1ps
module test();
    reg                     key_in_tb      ;

    wire                    led_out_tb     ; 

led led_insert(
    .key_in                 ( key_in_tb  ) ,

    .led_out                ( led_out_tb )     
);

    initial begin
        key_in_tb = 1'b1 ;
    end

    always #(20) key_in_tb <= ($random) % 2 ;

endmodule