112,Verilog-2005标准篇:Command line input(命令行输入)

开发人员除了通过读取文件来获取仿真的信息外,还可以通过调用仿真器的命令来指定信息,这些信息是以可选参数的形式提供给仿真器的。这些参数以加号 ( + ) 字符开头,与其他仿真器参数有明显区别,这些参数在下文中称为plusargs。

实现命令行输入功能的函数有两个:

- $test$plusargs

该系统函数会在plusargs列表中搜索用户指定的plusarg字符串。该字符串在系统函数的参数中指定为字符串或可解释为字符串的非实数变量。该字符串不得包含命令行参数的前导加号。命令行中的 plusargs 将按照提供的顺序进行搜索。如果所提供的某个plusargs的前缀与所提供字符串中的所有字符匹配,函数将返回一个非零整数。如果命令行中没有任何plusarg与所提供的字符串匹配,函数返回的整数值为零。

例如:使用命令“+HELLO”运行仿真器时,如果有如下的verilog代码:

则仿真器会产生如下输出:

- $value$plusargs

$value$plusarg系统函数会在plusargs列表(类似于 $test$plusargs 系统函数)中搜索用户指定的plusarg字符串。该字符串在系统函数的第一个参数中指定为一个字符串或一个可解释为字符串的非实数变量,该字符串不应包括命令行参数的前导加号。命令行中的 plusargs 将按照提供的顺序进行搜索。如果提供的某个plusargs的前缀与提供的字符串中的所有字符匹配,函数将返回一个非零整数,字符串的剩余部分将转换为user_string中指定的类型,并将结果值存储到提供的变量中。如果没有找到匹配的字符串,函数将返回一个非零整数,并且不修改所提供的变量。函数返回0时不会产生警告。

在提供给仿真器的plusarg列表中,与指定的user_string的plusarg_string部分相匹配的第一个字符串,就是可供转换的plusarg字符串。匹配的plusarg的剩余字符串(剩余字符串是plusarg字符串中与用户plusarg_string匹配部分之后的部分)应从字符串转换为格式字符串所指示的格式,并存储在所提供的变量中。如果没有剩余的字符串,存储到变量中的值应为 0 或空字符串值。

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Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Tue Jul 22 15:29:28 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: add_files SmoothProfileOnXAxisMean.cpp WARNING: [HLS 200-40] Cannot find design file 'SmoothProfileOnXAxisMean.cpp' INFO: [HLS 200-1510] Running: add_files SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean.h INFO: [HLS 200-10] Adding design file 'SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean.h' to the project INFO: [HLS 200-1510] Running: add_files -tb SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean_test.cpp -cflags -Wno-unknown-pragmas INFO: [HLS 200-10] Adding test bench file 'SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution solution2 -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 0.35ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1464] Running solution command: config_export -display_name=SmoothProfileOnXAxisMean INFO: [HLS 200-1464] Running solution command: config_export -format=ip_catalog INFO: [HLS 200-1464] Running solution command: config_export -library=KU060_200M_II1_NoGray_WIN33_250721 INFO: [HLS 200-1464] Running solution command: config_export -output=D:/HLS/SmoothProfileOnXAxisMean INFO: [HLS 200-1464] Running solution command: config_export -rtl=verilog INFO: [HLS 200-1464] Running solution command: config_export -vendor=WEIGUO INFO: [HLS 200-1464] Running solution command: config_export -version=2.5 INFO: [HLS 200-1464] Running solution command: config_cosim -tool=xsim INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: config_export -display_name SmoothProfileOnXAxisMean -format ip_catalog -library KU060_200M_II1_NoGray_WIN33_250721 -output D:/HLS/SmoothProfileOnXAxisMean -rtl verilog -vendor WEIGUO -version 2.5 INFO: [HLS 200-1510] Running: config_cosim -tool xsim INFO: [HLS 200-1510] Running: set_clock_uncertainty 0.35 INFO: [HLS 200-1510] Running: source ./SmoothProfileOnXAxisMean_NoGray/solution2/directives.tcl INFO: [HLS 200-1510] Running: set_directive_top -name SmoothProfileOnXAxisMean SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling ../../../src/SmoothProfileOnXAxisMean_test.cpp in debug mode Generating csim.exe Makefile.rules:317: recipe for target 'csim.exe' failed In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../src/SmoothProfileOnXAxisMean_test.cpp:3: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../src/SmoothProfileOnXAxisMean_test.cpp:3: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 obj/SmoothProfileOnXAxisMean_test.o: In function `main': G:\vitis2023_project\SmoothProfileOnXAxisMean_NoGray\solution2\csim\build/../../../src/SmoothProfileOnXAxisMean_test.cpp:59: undefined reference to `SmoothProfileOnXAxisMean(hls::stream<float, 0>&, hls::stream<float, 0>&, ap_uint<6>, float)' collect2.exe: error: ld returned 1 exit status make: *** [csim.exe] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s). INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 2.536 seconds; current allocated memory: 0.371 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 0 seconds. Total elapsed time: 4.239 seconds; peak allocated memory: 199.672 MB. Finished C simulation.
最新发布
07-23
" 信号对齐脚本 by 数字IC设计工程师 function! AlignSignalDeclarations() range let l:max_type_len = 0 let l:max_signal_len = 0 let l:entries = [] " 第一阶段:分析代码结构 for l:line in getline(a:firstline, a:lastline) " 清除行首空白并匹配关键结构 let l:clean_line = substitute(l:line, '^\s*', '', '') let l:parts = matchlist(l:clean_line, \ '^\(\S.*\S\)\s\+\(\S\+\)\s*;\(.*\)$') if empty(l:parts) call add(l:entries, {'valid': 0, 'line': l:line}) continue endif " 提取类型、信号名、注释 let l:type = substitute(l:parts[1], '\s\+', ' ', 'g') " 合并多余空格 let l:signal = l:parts[2] let l:comment = l:parts[3] " 更新最大长度 let l:max_type_len = max([l:max_type_len, strlen(l:type)]) let l:max_signal_len = max([l:max_signal_len, strlen(l:signal)]) call add(l:entries, { \ 'valid': 1, \ 'type': l:type, \ 'signal': l:signal, \ 'comment': l:comment}) endfor " 第二阶段:生成对齐代码 let l:formatted = [] for l:entry in l:entries if !l:entry.valid call add(l:formatted, l:entry.line) continue endif " 构建对齐行(Type + 2空格 + Signal + 对齐分号) let l:fmt = '%-' . l:max_type_len . 's %-' . l:max_signal_len . 's;%s' let l:new_line = printf(l:fmt, \ l:entry.type, \ l:entry.signal, \ l:entry.comment) call add(l:formatted, l:new_line) endfor " 第三阶段:替换原始内容 call setline(a:firstline, l:formatted) endfunction " 使用说明:选中代码块后执行以下命令 command! -range=% AlignSignals <line1>,<line2>call AlignSignalDeclarations() 优化上面的脚本, 要求保持原有的功能外,要处理位宽左右无空格的情况,行尾的注释要左对齐
03-29
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