
AG576 Low Power CPLDs is the lowest cost CPLDs. This instant-on, non-volatile CPLD family targets general-purpose and low-density logic. The logic density is 576 Logic Elements with LQFP-100 and 144 package.
Low-Cost and low-power CPLD with 1.8V core voltage (VCCINT)
Instant-on, non-volatile standard compatible architecture.
Up to 4 global clock lines in the global clock network that drive throughout the entire device.
Provides programmable fast propagation delay and clock-to-output times.
Provides PLL per device, clock multiplication, and phase shifting.
UFM supports non-volatile storage up to 256 Kbits.
Supports 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic level
Programmable slew rate, drive strength, bus-hold, programmable pull-up resistors, open-drain output, Schmitt triggers and programmable input delay.
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry complaint with IEEE Std. 1149.1-1990
ISP circuitry compliant with IEEE Std. 1532
3.3-V, 2.5-V, 1.8-V, 1.5-V LVCMOS and LVTTL standards
Emulated LVDS output (LVDS_E_3R)
Emulated RSDS output (RSDS_E_3R)
AG576LowPowerCPLD是最低成本的CPLD,具有即时启动、非易失性标准兼容架构,适用于通用和低密度逻辑应用。该设备提供576个逻辑元件,支持1.8V核心电压,具有4条全球时钟线路,内置PLL,支持高达256Kbits的非易失性存储,以及多种逻辑电平标准。
303

被折叠的 条评论
为什么被折叠?



