Low cost&Low Power CPLD Series

Embeded_FPGA

于 2021-07-07 11:12:33 发布

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分类专栏： CPLD 文章标签：机器学习自然语言处理深度学习自动驾驶数据挖掘

本文链接：https://blog.youkuaiyun.com/Embeded_FPGA/article/details/118542588

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本文介绍了AG256、AG576和AG1280等超低成本、低功耗CPLD产品。这些CPLD家族针对通用和低密度逻辑设计，具有即时启动、非易失性兼容架构，支持不同电压逻辑等级，内置JTAG边界扫描测试电路和ISP电路，提供多种输出选项，并具有低功耗特性。

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AG256

AG256 CPLDs is the low cost CPLDs. This instant-on, non-volatile CPLD family targets general-purpose and low-density logic. The logic density is 256 Logic Elements with LQFP-100 package.

Low-Cost and low-power CPLD
Instant-on, non-volatile standard compatible architecture.
Up to 4 global clock lines in the global clock network that drive throughout the entire device.
Provides programmable fast propagation delay and clock-to-output times.
UFM supports non-volatile storage up to 256 Kbits.
Supports 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic level
Programmable slew rate, drive strength, bus-hold, programmable pull-up resistors, open-drain output, Schmitt triggers and programmable input delay.
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry complaint with IEEE Std. 1149.1-1990
ISP circuitry compliant with IEEE Std. 1532
3.3-V, 2.5-V, 1.8-V, 1.5-V LVCMOS and LVTTL standards
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