AGM CPLD(AG256/272/576)介绍

最新推荐文章于 2024-03-03 15:43:32 发布

llisq

最新推荐文章于 2024-03-03 15:43:32 发布

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分类专栏： CPLD FPGA 文章标签： fpga/cpld

本文链接：https://blog.youkuaiyun.com/llisq/article/details/118530530

AGMCPLD家族包括AG256、AG272和AG576，它们是具有即时启动和非易失性的低成本CPLD，提供256至576个LUT和256Kbits的UFM。这些器件支持多种电压等级，具备可编程特性，如时钟管理、输入延迟等，并具有ISP和JTAG功能，广泛应用于各种应用中。

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AGM CPLD family provides low-cost instant-on, non-volatile CPLDs, with densities from 256, 272 to 576 logic LUTs and non-volatile flash storage of 256Kbits. The devices offer up to 144 I/O pins featuring with a user flash memory (UFM), and in-system programming. The devices are designed to reduce cost and power while providing programmable solutions for a wide range of applications.

Features:

 Low-Cost and low-power CPLD
 Instant-on, non-volatile Compatible FPGA architecture.
 Up to 4 global clock lines in the global clock network that drive throughout the entire device.
 Provides programmable fast propagation delay and clock-to-output times.
 Provides PLL per device provide clock multiplication and phaseshifting (AG256 has no PLL).
 UFM supports non-volatile storage up to 256 Kbits.
 Supports 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic level
 Programmable slew rate, drive strength, bus-hold, programmable pull-up resistors, open-drain output, Schmitt triggers and programmable input delay.
 Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry complaint with IEEE Std. 1149.1-1990
 ISP circuitry compliant with IEEE Std. 1532
 3.3-V, 2.5-V, 1.8-V, 1.5-V LVCMOS and LVTTL standards

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