UVM实战练习

本文记录了在使用UVM过程中遇到的一些问题及解决方法,包括import uvm_pkg:: 的遗漏导致的错误,dump波形到Verdi时的警告和错误,未指定endclass的报错,UVM_NOPACK操作影响,以及timescale问题及其解决策略。

摘要生成于 C知道 ,由 DeepSeek-R1 满血版支持, 前往体验 >

1、import uvm_pkg:: ;忘了写;。结果导致报错:System verilog keyword ‘class’ is not expected to be used in this context
2、dump波形到verdi的坎坷之路
2.1 -fsdb 和 -P xxx/novas.tab xxx…/pli.a同时加到option中,会包系统函数重复的warning。后来看了下是因为- fsdb -debug_access -P这三种都可以实现dump波形的功能,我估计是用了两个导致的warning。
2.2 报错dumping vcs annotated stack。原因有两个第一个是因为没有在vcs的option中加-full64,导致使用了32bit的vcs,但是-P的时候使用的是64bit的NOVAS的pli接口。后来将-P改成32bit的NOVAS就没有报错了,最后加上-full64并在-P中使用64bit的NOVAS也可以正常使用。
2.3 vcs没有报错,但是fsdb是空的没有波形。看了下novas_dump.log文件,其中有报错,它爆出了我$fsdbDunpvars([depth,][instance][,option]
)的第二个参数错误。有两种解决方法:
一是首先生产vcd文件,然后通过命令转成fsdb文件.
$dumpfile(“top.vcd”);
$dumpvars(0,top);
vcd2fsdb fsdbfile
第二种就是加-debug_pp选项
3、一个class没有加endclass的报错
创建了一个sequence的class,但是忘记写endclass了,导致使用这个sequence的时候报错:不是一个type。没有直接报sequence本身的问题。检查了很久的代码才发现这个问题。(如果怀疑前面定义的东西有问题,可以将其复制到当

Table of Contents Articles Introduction 0 Cookbook/Introduction 0 Cookbook/Acknowledgements 1 Testbench Architecture 2 Testbench 2 Testbench/Build 9 Testbench/Blocklevel 19 Testbench/IntegrationLevel 29 Component 39 Agent 42 Phasing 48 Factory 53 UsingFactoryOverrides 56 SystemVerilogPackages 62 Connections to DUT Interfaces 65 Connections 65 SVCreationOrder 71 Connect/SystemVerilogTechniques 73 ParameterizedTests 75 Connect/Virtual Interface 78 Config/VirtInterfaceConfigDb 86 Connect/VirtInterfacePackage 90 Connect/VirtInterfaceConfigPkg 93 Connect/TwoKingdomsFactory 97 DualTop 103 VirtInterfaceFunctionCallChain 106 BusFunctionalModels 108 ProtocolModules 111 Connect/AbstractConcrete 115 Connect/AbstractConcreteConfigDB 118 Configuring a Test Environment 126 Configuration 126 Resources/config db 131 Config/Params Package 134 Config/ConfiguringSequences 139 ResourceAccessForSequences 142 MacroCostBenefit 145 Analysis Components & Techniques 146 Analysis 146 AnalysisPort 149 AnalysisConnections 152 MonitorComponent 158 Predictors 161 Scoreboards 163 MetricAnalyzers 170 PostRunPhases 172 Matlab/Integration 175 End Of Test Mechanisms 183 EndOfTest 183 Objections 185 Sequences 188 Sequences 188 Sequences/Items 193 Transaction/Methods 195 Sequences/API 200 Connect/Sequencer 204 Driver/Sequence API 206 Sequences/Generation 213 Sequences/Overrides 221 Sequences/Virtual 223 Sequences/VirtualSequencer 231 Sequences/Hierarchy 237 Sequences/SequenceLibrary 242 Driver/Use Models 246 Driver/Unidirectional 247 Driver/Bidirectional 250 Driver/Pipelined 255 Sequences/Arbitration 267 Sequences/Priority 276 Sequences/LockGrab 277 Sequences/Slave 284 Stimulus/Signal Wait 290 Stimulus/Interrupts 294 Sequences/Stopping 301 Sequences/Layering 302 Register Abstraction Layer 308 Registers 308 Registers/Specification 315 Registers/Adapter 317 Registers/Integrating 321 Registers/Integration 327 Registers/RegisterModelOverview 332 Registers/ModelStructure 334 Registers/QuirkyRegisters 344 Registers/ModelCoverage 349 Registers/BackdoorAccess 354 Registers/Generation 357 Registers/StimulusAbstraction 358 Registers/MemoryStimulus 370 Registers/SequenceExamples 375 Registers/BuiltInSequences 382 Registers/Configuration 386 Registers/Scoreboarding 389 Registers/FunctionalCoverage 395 Testbench Acceleration through Co-Emulation 401 Emulation 401 Emulation/SeparateTopLevels 404 Emulation/SplitTransactors 410 Emulation/BackPointers 415 Emulation/DefiningAPI 419 Emulation/Example 422 Emulation/Example/APBDriver 430 Emulation/Example/SPIAgent 435 Emulation/Example/TopLevel 441 Debug of SV and UVM 444 BuiltInDebug 444 Reporting/Verbosity 455 UVM/CommandLineProcessor 460 UVM Connect - SV-SystemC interoperability 464 UvmConnect 464 UvmConnect/Connections 466 UvmConnect/Conversion 468 UvmConnect/CommandAPI 472 UVM Express - step by step improvement 476 UvmExpress 476 UvmExpress/DUT 481 UvmExpress/BFM 485 UvmExpress/WritingBfmTests 490 UvmExpress/FunctionalCoverage 498 UvmExpress/ConstrainedRandom 503 Appendix - Deployment 516 OVM2UVM 516 OVM2UVM/DeprecatedCode 527 OVM2UVM/SequenceLibrary 528 OVM2UVM/Phasing 530 OVM2UVM/ConvertPhaseMethods 535 UVC/UvmVerificationComponent 537 Package/Organization 548 Appendix - Coding Guidelines 555 SV/Guidelines 555 UVM/Guidelines 569 Appendix - Glossary of Terms 579 Doc/Glossary 579
评论
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值