uvm_lab2的代码几乎是从sv_lab5中移植出来的,主要包括sv的验证环境结构、组件之间的通信、激励产生和发送模式、数据检查和报告、测试开始和结束以及sv的配置方式;转移到uvm中,主要是掌握各个组件的使用,组件之间的验证关系、工厂的注册和创建、域自动化和uvm_object的预先定义方法、phase的自动执行和顺序、消息宏的简单使用、利用config_db对接口的传递、测试的选择和开始已经对仿真的控制。
实现组件的对应原则:
| SV | UVM |
| transaction类 | uvm_squence_item |
| drive类 | uvm_drive |
| generator类 | uvm_sequence +uvm_sequencer |
| monitor类 | uvm_monitor |
| agent类 | uvm_agent |
| env类 | uvm_env |
| checker类 | uvm_scoreboard类 |
| reference_model类和coverage_model类 | uvm_component |
| test类 | uvm_test |
以chnl_pkg为例,上面是SV部分,下面是UVM部分代码。
package chnl_pkg;
class chnl_trans;
rand bit[31:0] data[];
rand int ch_id;
rand int pkt_id;
rand int data_nidles;
rand int pkt_nidles;
bit rsp;
constraint cstr{
soft data.size inside {[4:32]};
foreach(data[i]) data[i] == 'hC000_0000 + (this.ch_id<<24) + (this.pkt_id<<8) + i;
soft ch_id == 0;
soft pkt_id == 0;
soft data_nidles inside {[0:2]};
soft pkt_nidles inside {[1:10]};
};
function chnl_trans clone();
chnl_trans c = new();
c.data = this.data;
c.ch_id = this.ch_id;
c.pkt_id = this.pkt_id;
c.data_nidles = this.data_nidles;
c.pkt_nidles = this.pkt_nidles;
c.rsp = this.rsp;
return c;
endfunction
function string sprint();
string s;
s = {s, $sformatf("=======================================\n")};
s = {s, $sformatf("chnl_trans object content is as below: \n")};
foreach(data[i]) s = {s, $sformatf("data[%0d] = %8x \n", i, this.data[i])};
s = {s, $sformatf("ch_id = %0d: \n", this.ch_id)};
s = {s, $sformatf("pkt_id = %0d: \n", this.pkt_id)};
s = {s, $sformatf("data_nidles = %0d: \n", this.data_nidles)};
s = {s, $sformatf("pkt_nidles = %0d: \n", this.pkt_nidles)};
s = {s, $sformatf("rsp = %0d: \n", this.rsp)};
s = {s, $sformatf("=======================================\n")};
return s;
endfunction
endclass: chnl_trans

本文详细介绍从System Verilog (SV)验证环境迁移到Universal Verification Methodology (UVM)的过程,包括组件映射、激励产生、响应监测及环境搭建等关键步骤。
最低0.47元/天 解锁文章
932

被折叠的 条评论
为什么被折叠?



