xilinx ultrascale+ ddr4 管脚约束规则 PG150

总结：

1）Address/control 是指： cs_n, ras_n (a16), cas_n (a15), we_n (a14), ba, bg, ck, cke, a, odt, act_n, and parity

2）FPGA BANK 有三个Byte lane按照T0\T1\T2\T3进行区分，每个lane包括N0-N12 共13个管脚，每个lane分成U和L两组 （nibble）。

3）dq[7:0]\dqs[0]\dm0 是一个通道，对应一个Byte lane,依次类推dq[15:8]\dqs[1]\dm1 对应一个通道；（For the x16, LDQS corresponds to the data on DQ[7:0]; UDQS corresponds to the data on DQ[15:8]. For the x4 and x8 con-figurations, DQS corresponds to the data on DQ[3:0] and DQ[7:0], respectively）；

4）对于X8和X16: dqs 必须放在每个通道的时钟专用管脚上（N6 and N7），dq必须放在同组的管脚上(除了N1和N12之外的同组管脚，其他没有强制顺序可以组内调线）;

5）对于X4：dqs 和 dq必须放在同组的U 或 L nibble 里：dqs如果在N0,N1 dq放在N2..N6,dqs放在 N6,N7 dq放在 N8..N11,（N12不能放dq，其他没有强制顺序可以组内调线)；

6）dm/dbi 必须放在N0管脚。

7）不同的lane 之间可以互换，但不能不同lane之间调线；

8）X4 内存颗粒必须成对使用，不能是奇数个颗粒使用，每个byte lane 里面的nibbles,划分必须是01，或者23.. ，不能是12.在一个byte里的nibble顺序可以调整。

9）Address/control 管脚必须放在一个BANK里（byte lanes），ck 管教对必须在其中一个byte lanes里

10）reset_n管脚满足电平和时钟约束即可，记得用电阻（4.7K）拉低

11）FPGA 同一个BANK可以让两个DDR4 IP核用，但是要满足AABB规则，即两个核调用的Byte lane别混叠。此时输入的reset必须共用一个。

13）Bank 不能不连续。

14）VREF 管脚接地（1K), VRP 240R接地。

15） 除了时钟和复位管脚，其他管脚不能在两种不同的bank类型中交叉布线（HP和HR bank,推荐HP）

16）Par alert_n TEN管脚不包含在FPGA管脚上，TEN 499R下拉到地，PAR Alert_n 39R上拉到VTT

17）如果该Bank 需要分配dq,dqs，sys_rst_n 信号不要放在N0 N6管脚上。

18）Important:同一个接口不要混用不同类型的芯片（X4 X8 X16）。

手册阅读记录：

规则1）：这个规则对Address/control进行了定义：

• Address/control means cs_n, ras_n (a16), cas_n (a15), we_n (a14), ba, bg, ck, cke, a, odt, act_n, and parity (valid for RDIMMs and LRDIMMs only). Multi-rank systems have one cs_n, cke, odt, and one ck pair per rank.

规则2）： 对FPGA管脚Byte lane分组进行了划分，Byte lane 按照T0\T1\T2..进行区分，每个lane保护N0-N12个管脚，每个lane分成U和L两组 （nibble）。

Pins in a byte lane are numbered N0 to N12.

Byte lanes in a bank are designed by T0, T1, T2, or T3. Nibbles within a byte lane are distinguished by a “U” or “L” designator added to the byte lane designator (T0, T1, T2, or T3). Thus they are T0L, T0U, T1L, T1U, T2L, T2U, T3L, and T3U.

如下图所示：根据管脚上的名称可以看到Byte lane 的分组信息T0..T4和每个组内的标号N0....N12;

规则3：dqs, dq, and dm/dbi location. （暗含规则：一组的放在一个lane通道上，如dq[7:0],dqs0 dm0是一个 associate，dq[15:8],dqs1 dm1是一个 associate）

a.对于X8和X16: dqs 必须放在每个通道的时钟专用管脚上（N6 and N7），dq必须放在同组的管脚上(除了N1和N12之外的同组管脚，其他没有强制顺序可以组内调线）;

b.对于X4：dqs 和 dq必须放在 同组的U 或 L nibble 里：dqs如果在N0,N1 dq放在N2..N6,dqs放在 N6,N7 dq放在 N8..N11,（N12不能放dq，其他没有强制顺序可以组内调线)

c.dm/dbi 必须放在N0管脚。

d. 对于X16内存颗粒，LDQS放在低位，UDQS放在高位，比如2颗芯片,第1颗芯片LDQS对应dqs[0];UDQS对应dqs[1],第2颗芯片LDQS对应dqs[2];UDQS对应dqs[3]，依次类推。Byte lane 和不同的assosite 信号没有强关联，可以调线。

a. Designs using x8 or x16 components – dqs must be located on a dedicated byte clock pair in the upper nibble designated with “U” (N6 and N7). dq associated with a dqs must be in same byte lane on any of the other pins except pins N1 and N12.

b. Designs using x4 components – dqs must be located on a dedicated byte clock pair in the nibble (N0 and N1 in the lower nibble, N6 and N7 in the upper nibble). dq associated with a dqs must be in same nibble on any of the other pins except pin N12 (upper nibble). The lower nibble dq and upper nibble dq must be allocated in the same byte lane.

c.dm/dbi must be on pin N0 in the byte lane with the associated dqs.

d. The x16 components must have the ldqs connected to the even dqs and the udqs must be connected to the ldqs + 1. The first x16 component has ldqs connected to dqs0 and udqs connected to dqs1 in the XDC file. The second x16 component has ldqs connected to dqs2 and udqs connected to dqs3. This pattern continues as needed for the interface. This does not restrict the physical location of the byte lanes. The byte lanes associated with the dqs’s might be moved as desired in the Vivado IDE to achieve optimal PCB routing.

2. X4 内存颗粒必须成对使用，不能是奇数个颗粒使用，每个byte lane 里面的nibbles,划分必须是01，或者23.. ，不能是12.在一个byte里的nibble顺序可以调整。

The x4 components must be used in pairs. Odd numbers of x4 components are not permitted. Both the upper and lower nibbles of a data byte must be occupied by a x4 dq/dqs group. Each byte lane containing two x4 nibbles must have sequential nibbles with the even nibble being the lower number. For example, a byte lane can have nibbles 0 and 1, or 2 and 3, but must not have 1 and 2. The ordering of the nibbles within a byte lane is not important.

4. Address/control can be on any of the 13 pins in the address/control byte lanes. Address/control must be contained within the same bank.

6. ck pair(s) must be on any PN pair(s) in the Address/Control byte lanes.

7.reset_n管脚满足电平和时钟约束即可，记得用电阻（4.7K）拉低： reset_n can be on any pin as long as general interconnect timing is met and I/O standard must be LVCMOS12. Reset to DRAM should be pulled down so it is held low during power up.

8. FPGA 同一个BANK可以让两个DDR4 IP核用，但是要满足AABB规则，即两个核调用的Byte lane别混叠。此时输入的reset必须共用一个。

Banks can be shared between two controllers. a. Each byte lane is dedicated to a specific controller (except for reset_n). b. Byte lanes from one controller cannot be placed inside the other. For example, with controllers A and B, “AABB” is allowed, while “ABAB” is not.

13. bank 不能不连续。Bank skipping is not allowed.

15.参考UG571对VREF 管脚接地（1K）： The dedicated VREF pins in the banks used for DDR4 must be tied to ground with a resistor value specified in the UltraScale™ Architecture SelectIO™ Resources User Guide (UG571) [Ref 7]. Internal VREF is required for DDR4.

16. 除了时钟和复位管脚，其他管脚不能在两种不同的bank类型中交叉布线（HP和HR bank,推荐HP）

The interface must be contained within the same I/O bank type (High Performance). Mixing bank types is not permitted with the exceptions of the reset_n in step #7 and the input clock mentioned in step #14.

17.Par alert_n TEN管脚不包含在FPGA管脚上，TEN 499R下拉到地，PAR Alert_n 39R上拉到VTT

The par input for command and address parity, alert_n input/output, and the TEN input for Connectivity Test Mode are not supported by this interface. Consult UltraScale Architecture PCB Design and Pin Planning User Guide (UG583) [Ref 11] on how to connect these signals when not used. For more information on parity errors, see the Address Parity, page 34.

19.sys_rst_n 信号不要放在N0 N6管脚上（如果该Bank 需要分配dq,dqs），

The system reset pin (sys_rst_n) must not be allocated to Pins N0 and N6 if the byte is used for the memory I/Os.

Important:每个接口不要混用不同类型的芯片。

Component interfaces should be created with the same component for all components in the interface. x16 components have a different number of bank groups than the x8 components. For example, a 72-bit wide component interface should be created by using nine x8 components or five x16 components where half of one component is not used. Four x16 components and one x8 component is not permissible.

发布于 2023-12-21 18:19・IP 属地北京