【【Systemverilog学习参考 简单的加法器验证-含覆盖率】】
adder.v
module adder (
input clk ,
input rst_n ,
input [3 : 0] in_0 ,
input [3 : 0] in_1 ,
input sel ,
output [3 : 0] out0 ,
output [3 : 0] out1 ,
output reg [4 : 0] out2
);
always@(posedge clk or negedge rst_n )
begin
if(rst_n == 0)
begin
out2 <= 0 ;
end
else
begin
out2 <= in_0 + in_1 ;
end
end
assign out1 = sel? in_1 : 0 ;
assign out0 = sel? in_0 : 0 ;
endmodule
adder_tb.sv
class play;
static int count = 0;
int id;
logic [2:0] ina;
logic [5 : 0] func_a;
int arr[6] = '{
0, 1, 2, 3, 4, 5};
function new();
this.id = count++;
endfunction
task showk();
foreach (arr