Mux256to1v HDLbits

新手刷题记录，方便自己学习，请大佬们多多指教
题目：
Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );

    assign out = in[sel*4 + 3: sel*4];
endmodule

然后提示：

Error (10734): Verilog HDL error at top_module.v(6): sel is not a constant File: /home/h/work/hdlbits.783911/top_module.v Line: 6

参考李锐博恩师兄，改为

assign out = {in[sel*4 + 3],in[sel*4 + 2],in[sel*4 + 1],in[sel*4]};

就对了

结论：in[sel4 + 3: sel4]里的sel必须上常数，在for循环中可以这么写