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RSS订阅原创 Verilog语法之延时
Verilog延时说明连续赋值中的延时LHS中加延时assign #2 y = ~a;assign #(2,3) y = ~a;assign #(2,3,4) y = ~a;LHS中加延时说明LHS: Left-Hand-Side，左式;RHS: Right-Hand-Side，右式;`timescale 1ns/100ps;连续赋值中的延时LHS中加延时assign #2 y = ~a;描述：非门的延时为2ns，输入端信号变化到输出端体现出来需要2ns时间。即a发生变化后，经过2ns
2022-05-29 17:38:04
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原创 HDLBits在线编程题之Mux256to1v
Exams/review2015 fancytimer题目代码题目地址：HDLBits-Mux256to1v介绍：vect [msb_expr:lsb_expr]的向量选择不支持变量，需要通过别的方式进行位选。代码// 方式1：用拼接操作符，适用于输出位宽小的情况module top_module( input [1023:0] in, input [7:0] sel, output [3:0] out ); assign out = {in[sel*4+3],
2022-04-24 20:28:57
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原创 HDLBits在线编程题之Exams/review2015 fancytimer
Exams/review2015 fancytimer题目代码题目地址：HDLBits-Exams/review2015 fancytimer介绍：花了好长时间写的，记录一下。将计数值量化为以1000为单位，开始时则有delay的1000需要计数。在couting过程中统计已经计了1000次的次数num_1k，将delay减去num_1k即count。代码module top_module ( input clk, input reset, // Synchronous
2021-10-30 18:28:02
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原创 HDLBits在线编程题之Exams/2013 q2bfsm
Exams/2013 q2bfsm题目代码题目地址：HDLBits-Exams/2013 q2bfsm介绍：花了好长时间写的，可惜还是没想出来如何减去最后一个状态E的使用。更新：状态图画得不好，导致用来打拍的寄存器量加起来比用来表示多个状态的寄存器变量还要多。具体状态图可以参考别人的做法。代码module top_module ( input clk, input resetn, // active-low synchronous reset input x,
2021-10-07 21:44:11
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原创 HDLBits在线练习题之Exams/2014 q3fsm
地址：HDLBits - Exams/2014 q3fsm介绍：仅记录代码module top_module ( input clk, input reset, // Synchronous reset input s, input w, output z); localparam A=1'b0,B=1'b1; reg current_state,next_state; always @(*) begin
2021-10-07 14:27:31
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原创 HDLBits在线练习题之Exams/ece241 2014 q5a
Exams/ece241 2014 q5a题目分析代码题目地址：HDLBits - Exams/ece241 2014 q5a详细：You are to design a one-input one-output serial 2’s complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of
2021-10-06 16:38:07
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原创 HDLBits在线练习题之FSM of Lemmings4
地址：HDLBits - Lemmings4介绍：仅记录代码module top_module( input clk, input areset, // Freshly brainwashed Lemmings walk left. input bump_left, input bump_right, input ground, input dig, output walk_left, output walk_right, o
2021-10-05 18:09:34
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原创 HDLBits在线练习题之Lemmings3
FSM of Lemmings3题目分析代码题目地址：HDLBits - Lemmings3详细：In addition to walking and falling, Lemmings can sometimes be told to do useful things, like dig (it starts digging when dig=1). A Lemming can dig if it is currently walking on ground (ground=1 and not
2021-10-05 16:35:31
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原创 HDLBits在线练习题之Lemmings2
FSM of Lemmings2题目分析代码题目地址：HDLBits - Lemmings2详细：In addition to walking left and right, Lemmings will fall (and presumably go “aaah!”) if the ground disappears underneath them.In addition to walking left and right and changing direction when bumped,
2021-10-05 13:25:24
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原创 HDLBits在线练习题之FSM of Water Level
Exams/ece241 2013 q4题目分析代码题目地址：HDLBits - FSM of water level详细： Also include an active-high synchronous reset that resets the state machine to a state equivalent to if the water level had been low for a long time (no sensors asserted, and all four outp
2021-10-04 18:04:21
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原创 HDLBits在线练习题之Countbcd
Countbcd题目分析代码题目地址：HDLBits - Countbcd详细：Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating
2021-09-12 22:57:57
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原创 HDLBits在线练习题之Exams/ece241 2014 q7b
Exams/ece241 2014 q7b题目分析代码题目类型: HDLBits在线练习题地址: https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q7b详细:From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters
2021-09-12 22:07:12
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